Patents by Inventor Koichi Nitta

Koichi Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5305341
    Abstract: According to this invention, in a semiconductor laser, an n-type InGaAlP cladding layer, an InGaP active layer, and a p-type InGaAlP cladding layer are sequentially grown on an n-type GaAs substrate to form a double hetero structure. The active layer is constituted by an ordered structure having regularity in the <111> directions, and the p-type cladding layer is constituted by a disordered structure. Band discontinuity in conduction band between the active layer and the p-type cladding layer is increased to improve the temperature characteristics of the laser.
    Type: Grant
    Filed: February 19, 1992
    Date of Patent: April 19, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukie Nishikawa, Koichi Nitta, Genichi Hatakoshi, Masaki Okajima, Minoru Watanabe, Kazuhiko Itaya
  • Patent number: 5282218
    Abstract: A semiconductor laser device for radiating a laser beam from a double heterostructure section in which injected carriers having an energy source of the laser beam are confined consists of a compound semiconductor substrate with a prescribed lattice constant for loading the double heterostructure section, a lattice mismatched active layer with a first lattice constant which is 0.5% to 2.0% larger than the lattice constant of the substrate in the double heterostructure section for radiating the laser beam, a lattice mismatched cladding layer with a second lattice constant which is 0.2% to 2.0% smaller than the lattice constant of the substrate for confining the injected carriers in the active layer, and a cladding layer for confining the injected carriers in the active layer by co-operating with the lattice mismatched cladding layer.
    Type: Grant
    Filed: June 9, 1992
    Date of Patent: January 25, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Okajima, Koichi Nitta, Genichi Hatakoshi, Yukie Nishikawa, Kazuhiko Itaya
  • Patent number: 5202895
    Abstract: A semiconductor laser device comprises a compound semiconductor substrate, a first cladding layer formed on the substrate, an active layer formed on the first cladding layer, made of In.sub.1-y (Ga.sub.1-x Al.sub.x).sub.y P material (0.ltoreq.x<1, 0.ltoreq.y<1), and a second cladding layer formed on the active layer. These first cladding layer, the active layer, and the second cladding layer forms a double heterostructure. A lattice constant of the active layer is larger than that of the substrate by 0.3% or more. The lattice constants of the first and second cladding layers are substantially equal to that of the substrate.
    Type: Grant
    Filed: May 3, 1991
    Date of Patent: April 13, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nitta, Masayuki Ishikawa, Yukie Nishikawa, Hideto Sugawara, Minoru Watanabe, Masaki Okajima, Genichi Hatakoshi
  • Patent number: 5058120
    Abstract: A visible light emitting semiconductor laser has a double-heterostructure section above the N-type GaAs substrate, which is composed of a nondoped InGaP active layer sandwiched between an N type InGaAlP cladding layer and a P type InGaAlP cladding layer. A P type InGaP thin-film layer formed on the P type cladding layer functions as an etching stopper. Formed sequentially on the etching stopper layer are a P type cladding layer and an N type GaAs current-blocking layer, which have a stripe-shaped groove section in and around their central portion. The groove section has an opening at the top and the bottom portion narrower than the opening, presenting an inverse-trapezoidal cross-sectional profile. This arrangement makes the width of the optical confinement region of the semiconductor laser narrower than that of the current injection region.
    Type: Grant
    Filed: December 27, 1990
    Date of Patent: October 15, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nitta, Yukio Watanabe, Yukie Nishikawa, Masaki Okajima, Genichi Hatakoshi
  • Patent number: 4987097
    Abstract: A gain waveguide type semiconductor laser oscillating visible light has an N type GaAs substrate of, and a double-heterostructure provided above the substrate to include an InGaP active layer, and first and second cladding layers sandwiching the active layer. The first cladding layer consists of N type InGaAlP, whereas the second cladding layer consists of P type InGaAlP. A P type InGaP layer is formed as an intermediate band-gap layer on the second cladding layer. An N type GaAs current-blocking layer is formed on the intermediate band-gap layer, and has an elongated waveguide opening. A P type GaAs contact layer is formed to cover the current-blocking layer and the opening.
    Type: Grant
    Filed: February 28, 1990
    Date of Patent: January 22, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nitta, Yukie Nishikawa, Masayuki Ishikawa, Yasuhiko Tsuburai, Yoshihiro Kokubun
  • Patent number: 4922499
    Abstract: A gain waveguide type semiconductor laser oscillating visible light has an N type GaAs substrate of, and a double-heterostructure provided above the substrate to include an InGap active layer, and first and second cladding layers sandwiching the active layer. The first cladding layer consists of N type InGaAlP, whereas the second cladding layer consists of P type InGaAlP. A P type InGaP layer is formed as an intermediate band-gap layer on the second cladding layer. An N type GaAs current-blocking layer is formed on the intermediate band-gap layer, and has an elongated waveguide opening. A P type GaAs contact layer is formed to cover the current-blocking layer and the opening.
    Type: Grant
    Filed: February 9, 1989
    Date of Patent: May 1, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nitta, Yukie Nishikawa, Masayuki Ishikawa, Yasuhiko Tsuburai, Yoshihiro Kokubun
  • Patent number: 4788931
    Abstract: A method of forming external electrodes at both ends of chip parts while elastically holding the chip parts.
    Type: Grant
    Filed: February 19, 1987
    Date of Patent: December 6, 1988
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koichi Nitta, Kazuma Kabuta, Masami Yamaguchi, Tadahiro Nakagawa, Katsuyuki Moriyasu
  • Patent number: 4746895
    Abstract: A ceramic electronic component which comprises a generally elongated ceramic body and a metal cap mounted on each end of the ceramic body. Each end of the ceramic body has a peripheral edge rounded to have a predetermined first radius of rounding, and the metal cap has an interior corner rounded to have a predetermined second radius of rounding. The first radius of rounding is greater than the second radius of rounding.
    Type: Grant
    Filed: November 18, 1986
    Date of Patent: May 24, 1988
    Assignee: Murata Mfg. Co., Ltd.
    Inventors: Toshikazu Kato, Koichi Nitta
  • Patent number: 4706101
    Abstract: A light emitting diode is disclosed which includes an N-GaAs substrate, a double hetero-junction structure obtained by forming an N-GaAlAs clad layer, a P-GaAs active layer and a P-GaAlAs clad layer on the substrate in that order, and a current narrowing structure obtained by selectively forming a contact metal on the P-GaAlAs clad layer in the double hetero-junction structure with the contact metal formed around the contact metal. In the light emitting diode so manufactured, the double hetero-junction structure is formed by a metal organic vapor deposition method. The N-GaAlAs clad layer is of a three-layer structure with one layer of a narrower forbidden band width sandwiched between the remaining two layers of a wider forbidden band width.
    Type: Grant
    Filed: August 20, 1985
    Date of Patent: November 10, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Nakamura, Masaki Okajima, Tadashi Komatsubara, Tetsuo Sadamasa, Koichi Nitta
  • Patent number: 4664943
    Abstract: A method of forming external electrodes at both ends of chip parts while elastically holding the chip parts.
    Type: Grant
    Filed: November 15, 1984
    Date of Patent: May 12, 1987
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koichi Nitta, Kazuma Kabuta, Masami Yamaguchi, Tadahiro Nakagawa, Katsuyuki Moriyasu
  • Patent number: 4514787
    Abstract: An electronic component series wherein a plurality of parallel lead type electronic components (1) each having two parallel lead wires (4) are equispaced along a retainer band (2) and distributed along the length of the retainer band (2) with the lead wires (4) extending in the same direction and are positioned by the retainer band (2), whereby the electronic components (1) are retained. The electronic component series is characterized in that the distance (A) between the pair of lead wires (4) of each electronic component (1) in a region (4a) where the lead wires (4) are placed on the retainer band (2) is made different from that (B) in a region (4c) closer to the electronic component main body (3), while the intermediate portions (4b) of the lead wires (4) are bent to absorb the difference in dimension between the distances (A, B).
    Type: Grant
    Filed: May 5, 1983
    Date of Patent: April 30, 1985
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Fumihiko Kaneko, Tetsuya Murakawa, Koichi Nitta, Noriaki Yamana, Masashi Takeda, Kunio Tachi
  • Patent number: 4298120
    Abstract: A chip-like electronic component series comprises a tape-like member formed with a plurality of apertures arranged in the longitudinal direction for receiving one by one a plurality of chip-like electronic components, cover sheets adhered to both surfaces of the tape-like member for sealing the apertures, and feeding perforations formed equispaced in the longitudinal direction of the tape-like member. The chip-like electronic component series is fed by using the feeding perforations, and the chip-like electronic components are supplied therefrom onto a print circuit board, for example, by stripping the upper cover and by pushing the electronic components one by one onto the print circuit board while the lower cover sheet is broken, by picking up the electronic components therefrom one by one, or the like to place the same onto the print circuit board.
    Type: Grant
    Filed: November 29, 1979
    Date of Patent: November 3, 1981
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Fumihiko Kaneko, Koichi Nitta, Kouichi Saito