Patents by Inventor Koichi Nose
Koichi Nose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170009312Abstract: The present invention has as its object to provide thickness 60 ?m or less ultra-thin stainless steel foil which secures high thickness precision and simultaneously secures plastic deformability and good elongation at break, that is, secures good press-formability (deep drawability). The present invention solves this problem by ultra-thin stainless steel foil which has three or more crystal grains in a thickness direction, has a recrystallization rate of 90% to 100%, and has a nitrogen concentration of a surface layer of 1.0 mass % or less. For this reason, there is provided a method of production of stainless steel foil comprising rolling stainless steel sheet, then performing final annealing and making a thickness 5 ?m to 60 ?m, wherein a rolling reduction ratio at rolling right before final annealing is 30% or more, a temperature of final annealing after rolling is 950° C. to 1050° C. in the case of austenitic stainless steel and 850° C. to 950° C.Type: ApplicationFiled: February 16, 2015Publication date: January 12, 2017Applicant: NIPPON STEEL & SUMIKIN MATERIALS CO., LTD.Inventors: Hiroto UNNO, Shinichi TERASHIMA, Toru INAGUMA, Koichi NOSE, Naoki FUJIMOTO, Naoya SAWAKI, Shuji NAGASAKI
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Publication number: 20160065070Abstract: According to one embodiment, a semiconductor device includes: a first switch SWx which switches whether or not to supply a first power supply voltage Vx generated by accumulating a charge outputted from a power source 10, as a second power supply voltage VDD to a first circuit 13, and a second switch SW1 which switches whether or not to connect to the first circuit 13 a smoothing capacitor C1 which suppresses a fluctuation of the second power supply voltage VDD, and the first switch SWx is switched to an on state in response to that the first power supply voltage Vx has reached a sufficient voltage, and then the second switch SW1 is switched to the on state in response to that the second power supply voltage VDD has reached a sufficient voltage.Type: ApplicationFiled: August 11, 2015Publication date: March 3, 2016Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Koichiro NOGUCHI, Koichi NOSE, Yoshifumi IKENAGA, Yoichi YOSHIDA
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Patent number: 9187814Abstract: The hot-dip aluminum alloy plated steel has a base steel and a plated layer, in which the composition of the plated layer contains, by % by mass, Fe: 25% to 75%, Mg: 2% to 20%, and Ca: 0.02% to 2% with a remainder of Al and inevitable impurities, the plated layer contains one or both of an ?-Mg phase and an Al3Mg2 phase, and the sum of the partial volume fraction of the ?-Mg phase and the partial volume fraction of the Al3Mg2 phase in a range of a depth of 5 ?m from a surface of the plated layer is 1% to 40%.Type: GrantFiled: May 31, 2011Date of Patent: November 17, 2015Assignee: NIPPON STEEL & SUMITOMO METAL CORPORATIONInventors: Koichi Nose, Yasuhide Morimoto, Kohei Tokuda
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Publication number: 20150311706Abstract: A power supply device according to an embodiment comprises a plurality of power sources 10 each including an antenna and an AC/DC conversion unit, a plurality of consolidating units 13—1 to 13—i, and a power supply unit 15. The consolidating units 13—1 to 13—i respectively include consolidating circuits 14—1 to 14—i that selectively consolidate a plurality of DC signals 21—1 to 21—n supplied by the plurality of power sources 10. The power supply unit 15 includes a consolidating circuit 16 that selectively consolidates the DC signals 21—1 to 21—i output from the plurality of consolidating units 13—1 to 13—i, and a voltage conversion circuit 17 that converts a DC signal 23 resulting from consolidation in the consolidating circuit 16, to a predetermined voltage.Type: ApplicationFiled: April 18, 2015Publication date: October 29, 2015Inventors: Koichiro NOGUCHI, Koichi NOSE, Yoshifumi IKENAGA, Yoichi YOSHIDA
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Publication number: 20150290618Abstract: An object of the present invention is to provide a porous polymer metal complex which can be used as a gas adsorbent and contains two or more types of similar ligands. A porous polymer metal complex is provided expressed by [CuX]n(1) (in the Formula, X represents two or more types of isophthalic acid ions selected from the group consisting of isophthalic acid ions and isophthalic acid ions having a substituent at position 5, at least an amount of one type of X is 5 mol % to 95 mol % of the total number of moles of X, and n represents an assembly number of constituent units expressed by CuX and is not particularly limited).Type: ApplicationFiled: October 31, 2013Publication date: October 15, 2015Applicants: KYOTO UNIVERSITY, NIPPON STEEL & SUMITOMO METAL CORPORATIONInventors: Hiroshi Kajiro, Koichi Nose, Susumu Kitagawa, Ryotaro Matsuda, Hiroshi Sato
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Publication number: 20150180239Abstract: There is a problem in the prior semiconductor devices that energy recovery efficiency is low. According to one embodiment of the present invention, a power supply circuit includes an alternating-current signal synthesis unit including a plurality of alternating-current coupling elements having primary sides to which respective input alternating-current signals are input and secondary sides connected in series with each other, and a control circuit that outputs an input selection signal specifying a combination of the input alternating-current signals to be synthesized. The control circuit generates the input selection signal so as to maximize the output alternating-current signal synthesized by the alternating-current synthesis signal unit.Type: ApplicationFiled: October 25, 2014Publication date: June 25, 2015Inventors: Koichiro NOGUCHI, Koichi Nose, Yoshifumi Ikenaga, Yoichi Yoshida
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Publication number: 20150030912Abstract: A resin-metal composite sealed container having a heat seal part using a heat-sealing resin, between an end part of a first metal foil and an end part of a second metal foil, and a metallically sealed part with a weld bead, on the end face outside the heat sealed part of the first metal foil and the second metal foil. The resin-metal composite sealed container, wherein the melting point of the metal constituting the metal foil is higher by 300° C. or more than the thermal decomposition temperature of the heat-sealing resin, the specific gravity of the metal constituting the metal foil is 5 or more, and the weld bead is formed by a laser welding.Type: ApplicationFiled: February 21, 2013Publication date: January 29, 2015Inventors: Koichi Nose, Jun Nakatsuka, Yutaka Matsuzawa, Yu Murai
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Publication number: 20140085951Abstract: Provided is a receiving circuit that operates in a power supply system different from a transmitting circuit outputting a transmission signal and receives the transmission signal through an AC coupling device where a primary coil through which the transmission signal flows and a secondary coil having a center tap to which a specified voltage is supplied from an external terminal are magnetically coupled, which includes a pulse width amplifier circuit that holds pulse signals appearing at both ends of the secondary coil for a specified period of time and outputs them as hold signals, respectively, and a differential amplifier that compares a voltage of the hold signal and a voltage of the hold signal and outputs a comparison result.Type: ApplicationFiled: April 5, 2012Publication date: March 27, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shunichi Kaeriyama, Kouichi Yamaguchi, Koichi Nose
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Patent number: 8674774Abstract: There is provided an aging diagnostic device including: a reference ring oscillator (101) that constitutes a ring oscillator using an odd-numbered plurality of logic gates constituted using a CMOS circuit; a test ring oscillator (102) that constitutes a ring oscillator using an odd-numbered plurality of logic gates having the same configuration as that of the logic gate; a load unit (104) that inputs a load signal to the test ring oscillator (102); a control unit (105) that simultaneously inputs a control signal instructing a start of oscillation of the reference ring oscillator (101) and the test ring oscillator (102) to the reference ring oscillator (101) and the test ring oscillator (102); and a comparison unit (103) that compares differences in the amount of movement of pulses within the reference ring oscillator (101) and the test ring oscillator (102), respectively, in the same time.Type: GrantFiled: September 1, 2010Date of Patent: March 18, 2014Assignee: NEC CorporationInventors: Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno
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Patent number: 8663818Abstract: The present invention provides a high corrosion resistance hot dip galvannealed steel material comprised of a Zn-based hot dip plated steel material achieving both a higher corrosion resistance of the plated layer itself by the added elements and sacrificial protection of iron metal by the plated layer or workability free of degradation caused of formation of intermetallic compounds by added elements, that is, a high corrosion resistance hot dip Zn plated steel material characterized in that an alloy plated layer containing Zn: 35 mass % or more, preferably 40 mass % or more, contains a non-equilibrium phase having a heat capacity by differential scanning calorimetry of 1 J/g or more. Furthermore, 5% or more, preferably 50% or more in terms of vol % is an amorphous phase. The alloy layer may contain, by mass %, Mg: 1 to 60% and Al: 0.07 to 59%, may further contain one or more elements selected from Cr, Mn, Fe, Co, Ni, and Cu in a total of 0.1 to 10%, and may in addition contain one or more elements of 0.Type: GrantFiled: March 14, 2007Date of Patent: March 4, 2014Assignee: Nippon Steel & Sumitomo Metal CorporationInventors: Koichi Nose, Kohei Tokuda, Yuichi Sato, Makoto Nakazawa
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Patent number: 8653861Abstract: A control voltage generating circuit according to an aspect of the present invention includes: a reference voltage unit that includes a plurality of first transistors of the same conductivity type connected in series between a first power supply and a second power supply, and generates a drain voltage of one of the plurality of first transistor as a reference voltage; and a voltage conversion unit that includes a plurality of second transistors connected in series between the first power supply and the second power supply and having the same conductivity type as that of the reference voltage, supplies the reference voltage to a gate of one of the plurality of second transistors, and outputs a drain voltage of one of the plurality of second transistors as a control voltage.Type: GrantFiled: September 9, 2011Date of Patent: February 18, 2014Assignee: Renesas Electronics CorporationInventors: Koichiro Noguchi, Koichi Nose
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Patent number: 8637163Abstract: An alloy with a high glass forming ability characterized by containing a group of elements A with atomic radii of less than 0.145 nm of a total of 20 to 85 atm %, a group of elements B with atomic radii of 0.145 nm to less than 0.17 nm of a total of 10 to 79.7 atm %, and a group of elements C with atomic radii of 0.17 nm or more of a total of 0.3 to 15 atm %; when the elements with the greatest contents in the group of elements A, group of elements B, and group of elements C are respectively designated as the “element a”, “element b”, and “element c”, by the ratio of the content of the element a in the group of elements A (for example, Zn and/or Al), the ratio of the content of the element b in the group of elements B (for example, Mg), and the ratio of the content of the element c in the group of elements C (for example, Ca) all being 70 atm % or more; and by the liquid forming enthalpy between any two elements selected from the element a, element b, and element c being negative.Type: GrantFiled: July 19, 2007Date of Patent: January 28, 2014Assignee: Nippon Steel & Sumitomo Metal CorporationInventors: Kohei Tokuda, Koichi Nose, Yuichi Sato, Makoto Nakazawa
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Patent number: 8635040Abstract: A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal.Type: GrantFiled: December 19, 2007Date of Patent: January 21, 2014Assignee: NEC CorporationInventors: Koichi Nose, Masayuki Mizuno, Atsufumi Shibayama
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Patent number: 8562757Abstract: An Mg-based alloy plated steel material superior in adhesion and corrosion resistance characterized by being provided with a hot dip Mg-based alloy plating layer (preferably containing Zn: 15 atm % to less than 45 atm %).Type: GrantFiled: March 14, 2008Date of Patent: October 22, 2013Assignee: Nippon Steel & Sumitomo Metal CorporationInventors: Kohei Tokuda, Koichi Nose
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Patent number: 8513970Abstract: A semiconductor device (1) includes a semiconductor wafer (11) on which a plurality of semiconductor chip forming regions (1A) is formed, a circuit section (12) which is provided within each of the semiconductor chip forming regions (1A) of the semiconductor wafer (11), a control circuit section (14), provided within each of the semiconductor chip forming regions (1A) and connected to the circuit section (12), that controls electric power supplied to the circuit section (12), a power supply line (18) connected to the plurality of control circuit section (14), and a reference power line (17) connected to the plurality of control circuit section (14). In each of the control circuit sections (14), a voltage of electric power supplied from the power supply line (18) is controlled on the basis of a reference voltage from the reference power line (17).Type: GrantFiled: December 22, 2009Date of Patent: August 20, 2013Assignee: NEC CorporationInventors: Yoshio Kameda, Yoshihiro Nakagawa, Koichiro Noguchi, Masayuki Mizuno, Koichi Nose
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Patent number: 8446162Abstract: A semiconductor integrated circuit device includes: a normal output signal counter that counts number of times a normal output signal is output by the circuit under test in response to a preset one of the input signals of the input signal set, in case where a circuit under test repeats processing on each of one or more input signals of an input signal set sequentially, a plural number of times.Type: GrantFiled: November 21, 2008Date of Patent: May 21, 2013Assignee: NEC CorporationInventors: Koichi Nose, Masayuki Mizuno
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Patent number: 8444316Abstract: Current reading means detects an output current of a current source whose output current varies with a variation in temperature and outputs a value proportional to the output current. The temperature of the current source corresponding to the output value of the current reading means which is proportional to the output current of the current source is measured, and a parameter for converting the output value to temperature information is determined from the output value of the current reading means and the measured value of the temperature of the current source corresponding to the output value. The output value of the current reading means is converted to the temperature information using the determined parameter.Type: GrantFiled: November 27, 2008Date of Patent: May 21, 2013Assignee: NEC CorporationInventors: Eisuke Saneyoshi, Koichi Nose, Mikihiro Kajita, Masayuki Mizuno
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Patent number: 8441277Abstract: A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.Type: GrantFiled: December 16, 2008Date of Patent: May 14, 2013Assignees: NEC Corporation, Renesas Electronics CorporationInventors: Koichiro Noguchi, Yoshio Kameda, Koichi Nose, Masayuki Mizuno, Toshinobu Ono
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Patent number: 8355884Abstract: Spectrum measurement circuit (101) includes: N-(where N is integer equal or greater than 2) phase clock generation circuit (304) for supplying phase-modulated signals in which the phase of a clock signal is shifted by a phase modulation amount each time the settings of the phase modulation amount are switched; mixer circuit (303) for taking the product of a measured signal supplied from a transmitter and the phase-modulated signals supplied from N-phase clock generation circuit (304); average value output circuit (305) for supplying an average voltage value of the output signal of mixer circuit (303); memory (307) for storing the average voltage value supplied from average value output circuit (305) for each phase modulation amount of N-phase clock generation circuit (304); and arithmetic unit (308) for using the average voltage value for each phase modulation amount of N-phase clock generation circuit (304) to calculate the signal strength of the measured signal.Type: GrantFiled: December 18, 2007Date of Patent: January 15, 2013Assignee: NEC CorporationInventors: Koichi Nose, Masayuki Mizuno
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Publication number: 20130002274Abstract: Provided is an aging degradation diagnosis circuit, including: a first delay circuit including a gate array for allowing aging degradation to progress, the first delay circuit being configured to delay an input signal and output a first output signal; a second delay circuit including a gate array having the same number of stages as the first delay circuit, the second delay circuit being configured to delay an input signal and output a second output signal; and an arbitrary delay unit, which is capable of varying a delay period in the second delay circuit by a predetermined amount. A delay comparison unit outputs comparison information obtained by relatively comparing delays between the first output signal and the second output signal. An adjustment unit uses the comparison information, to thereby readjust the delay period in the second delay circuit.Type: ApplicationFiled: March 11, 2011Publication date: January 3, 2013Applicant: NEC CorporationInventors: Eisuke Saneyoshi, Koichi Nose