Abstract: A semiconductor integrated circuit device includes: a normal output signal counter that counts number of times a normal output signal is output by the circuit under test in response to a preset one of the input signals of the input signal set, in case where a circuit under test repeats processing on each of one or more input signals of an input signal set sequentially, a plural number of times.

Abstract: Disclosed is a semiconductor integrated circuit including a first storage circuit and a second storage circuit that respectively store logic levels of an input to the delay circuit and an output of the delay circuit when a logic level of a clock line is changed, and a determination circuit that determines whether or not the results of the first storage circuit and the second storage circuit coincide or not. Even if a transistor or a wiring that constitutes the semiconductor integrated circuit has been degraded due to secular change or the like, a possibility of an anomaly or a failure in one of the operation circuits caused by the degradation can be predicted before the anomaly or the failure occurs.

Abstract: Provided is a modulation device including a signal selection circuit selecting two carrier signals from a plurality of carrier signals having the same frequency and the same phase difference according to a defined control signal and outputting the selected carrier signals, and a phase interpolator adjusting the phase in smaller units than the phase difference between the plurality of carrier signals according to the control signal and modulating the frequency or the phase of the carrier signal into a baseband signal based on the carrier signals selected by the signal selection circuit to generate a carrier wave signal.

Abstract: A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.

Abstract: The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and high reliability. An object of the present invention is to provide a semiconductor device with high reliability, by analyzing factors affecting the performance of the semiconductor device, based on the communication histories within the semiconductor device, and reflecting the analysis back to the next generation semiconductor devices. The improved semiconductor device includes a core A for transmitting data in sync with the clock signal clkA, a core B for receiving data in sync with the clock signal clkB coincided with the rising or falling of the clock signal clkA in a constant period, and a controller for controlling communications between the core A and the core B.

Abstract: Spectrum measurement circuit (101) includes: N- (where N is integer equal or greater than 2) phase clock generation circuit (304) for supplying phase-modulated signals in which the phase of a clock signal is shifted by a phase modulation amount each time the settings of the phase modulation amount are switched; mixer circuit (303) for taking the product of a measured signal supplied from a transmitter and the phase-modulated signals supplied from N-phase clock generation circuit (304); average value output circuit (305) for supplying an average voltage value of the output signal of mixer circuit (303); memory (307) for storing the average voltage value supplied from average value output circuit (305) for each phase modulation amount of the N-phase clock generation circuit (304); and arithmetic unit (308) for using the average voltage value for each phase modulation amount of N-phase clock generation circuit (304) to calculate the signal strength of the measured signal.

Abstract: [PROBLEMS] To provide, for example, a pulse input type power amplifying apparatus that can be operated at low voltage and low power, effectively suppressing generation of harmonic component. [MEANS FOR SOLVING THE PROBLEMS] The amplifying apparatus includes at least two amplification circuits, one and other amplification circuits, composed of multiple amplifiers whose output sides are connected to each other, driven at the same frequency. The multiple amplifiers forming the one amplification circuit are configured with a first inverting amplifier M12 inputting and amplifying a reference pulse, and a second inverting amplifier M11 to which an inverted pulse formed by shifting and inverting the phase of the reference pulse is inputted. The other amplification circuit is configured with the first inverting amplifier M14 and the second inverting amplifier M13 to each of which other wide pulse with a width greater than that of the reference pulse is commonly inputted.

Abstract: A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an input clock signal CKI to output an output clock signal CKO; and a variable delay control circuit which cumulatively adds values obtained by subtracting N from M every cycle of the input clock signal CKI, when the addition result is N or more, performs a calculation which subtracts N from the addition result to obtain a calculation result K, and calculates, to a maximum delay amount in the variable delay circuit corresponding to one cycle of the input clock signal CKI, a control value corresponding to a delay amount of K/N of the maximum delay amount to give the control value to the variable delay circuit.

Abstract: To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and Mare integers, includes an output clock selecting circuit (200) that selects one of three situations: an input clock signal is outputted as it is, the input clock signal is inverted and outputted and the input clock signal is not outputted; and a clock selection control circuit (100) that generates a control signal for controlling the foregoing selection of the output clock selecting circuit. The clock selection control circuit controls the foregoing selection of the output clock selecting circuit at every cycle of the input clock signal.

Abstract: A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal.

Abstract: An Mg-based alloy plated steel material superior in adhesion and corrosion resistance characterized by being provided with a hot dip Mg-based alloy plating layer (preferably containing Zn: 15 atm % to less than 45 atm %).

Abstract: A light receiving circuit (114) includes a light inputting circuit (113) which converts one-system optical signal to be outputted from an optical transmission path (101) to an electrical signal and inverts a potential of the electrical signal each time the optical signal is detected, and a buffer circuit (110) which amplifies the electrical signal converted by the light inputting circuit and outputs the same. According to such configuration, since one-system optical signal may be inputted to the light receiving circuit, a system circuit configuration can be avoided to be complicated.

Abstract: Small-scale measuring circuits (111-1qum) are arranged in m columns×q rows. The small-scale measuring circuits of each row (111-11m, 121-12m, 1q1-1qm) are connected in series. The respective rows are connected in parallel. Supplying reference signals B having different parameter values to the small-scale measuring circuits (111-11m, . . . ) connected in series makes it possible to improve the measurement range or measurement resolution. Supplying reference signals B having the same parameter to the respective rows can reduce a noise component depending on the transistor size. According to this invention, using a plurality of small-scale measuring circuits in accordance with required measurement performance concerning a measurement range, resolution, noise reduction, or the like can implement the desired performance while minimizing the area of each measuring circuit.

Abstract: An alloy with a high glass forming ability characterized by containing a group of elements A with atomic radii of less than 0.145 nm of a total of 20 to 85 atm %, a group of elements B with atomic radii of 0.145 nm to less than 0.17 nm of a total of 10 to 79.7 atm %, and a group of elements C with atomic radii of 0.17 nm or more of a total of 0.3 to 15 atm %; when the elements with the greatest contents in the group of elements A, group of elements B, and group of elements C are respectively designated as the “element a”, “element b”, and “element c”, by the ratio of the content of the element a in the group of elements A (for example, Zn and/or Al), the ratio of the content of the element b in the group of elements B (for example, Mg), and the ratio of the content of the element c in the group of elements C (for example, Ca) all being 70 atm % or more; and by the liquid forming enthalpy between any two elements selected from the element a, element b, and element c being negative.

Abstract: A control signal input circuit for supplying control signals to a plurality of controlled circuits comprises N pieces of control signal preservation/output circuits provided one by one corresponding to plural-bit signals for delivering input data as it is when a trigger signal is at a first level, and holding previously delivered output data when the trigger signal is at a second level, and a controlled circuit selector circuit for setting the trigger signal for S pieces of the control signal preservation/output circuits to the first level, and setting the trigger signal for the rest of the control signal preservation/output circuits to the second level.

Abstract: An interpolated signal generating circuit (101) generates interpolated signals (SIG1-SIGN) of two consecutive discrete signals (SIG). N measuring circuits (501) measure interpolated signals. Since the interpolated signals are measurement targets, N-times oversampling measurement can also be performed for the discrete signals. With the oversampling measurement, the frequency spectra of the signal components of the discrete signals are maintained, and only the frequency spectrum of a noise component due to a quantization error increases to a high-frequency band, thereby reducing a noise component per unit frequency. Therefore, removing a high-frequency component from a measurement result from each measuring circuit using a low-pass filter (502) makes it possible to improve the signal-to-noise ratio of the measurement result as compared with a case in which no oversampling is performed.

Abstract: A phase difference measuring device according to this invention has an object of shortening the measuring time, and includes a plurality of phase difference measuring circuits (104, 105, 106) formed in a row, and phase difference conversion circuits (101, 102, 103) each connected between adjacent phase difference measuring circuits. The phase difference measuring circuit receives first and second signals, respectively gives the first and second signals first and second delay amounts cumulatively a plurality of number of times, and, whenever giving the delay amounts, compares the phases of the first and second signals given the delay amounts, thereby determining which one of the phases leads the other.

Abstract: The present invention provides a high corrosion resistance hot dip galvannealed steel material comprised of a Zn-based hot dip plated steel material achieving both a higher corrosion resistance of the plated layer itself by the added elements and sacrificial protection of iron metal by the plated layer or workability free of degradation caused of formation of intermetallic compounds by added elements, that is, a high corrosion resistance hot dip Zn plated steel material characterized in that an alloy plated layer containing Zn: 35 mass % or more, preferably 40 mass % or more, contains a non-equilibrium phase having a heat capacity by differential scanning calorimetry of 1 J/g or more. Furthermore, 5% or more, preferably 50% or more in terms of vol % is an amorphous phase. The alloy layer may contain, by mass %, Mg: 1 to 60% and Al: 0.07 to 59%, may further contain one or more elements selected from Cr, Mn, Fe, Co, Ni, and Cu in a total of 0.1 to 10%, and may in addition contain one or more elements of 0.

Abstract: The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and high reliability. An object of the present invention is to provide a semiconductor device with high reliability, by analyzing factors affecting the performance of the semiconductor device, based on the communication histories within the semiconductor device, and reflecting the analysis back to the next generation semiconductor devices. The improved semiconductor device includes a core A for transmitting data in sync with the clock signal clkA, a core B for receiving data in sync with the clock signal clkB coincided with the rising or falling of the clock signal clkA in a constant period, and a controller for controlling communications between the core A and the core B.

Abstract: A clock converting circuit (1) receives and then converts m-phase clocks of a frequency f having a phase difference of 1/(f×m) to n-phase clocks of the frequency f having a phase difference of 1/(f×n). A single-phase clock generating circuit (2) receives the n-phase clocks of the frequency f having a phase difference equivalent time of 1/(f×n) to generate single-phase clocks in synchronism with the rising or falling edges of the n-phase clocks. Since the frequency of the m-phase clocks inputted to the clock converting circuit (1) is ‘f’, if a desired frequency of the single-phase clocks is decided, then ‘n’ can be obtained from the equation: the frequency of the single-phase clocks is equal to (f×n). This value of ‘n’ is set to the clock converting circuit (1), thereby obtaining the n-phase clocks of the frequency f from the m-phase clocks of the frequency f to provide single-phase clocks of a desired frequency.