Patents by Inventor Koichi Tachibana
Koichi Tachibana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140346439Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting part, and a multilayered structural body. The light emitting part is provided between the first and second semiconductor layers and includes barrier layers and well layers alternately stacked. The multilayered structural body is provided between the first semiconductor layer and the light emitting part and includes high energy layers and low energy layers alternately stacked. An average In composition ratio on a side of the second semiconductor is higher than that on a side of the first semiconductor in the multilayered structural body. An average In composition ratio on a side of the second semiconductor is higher than that on a side of the first semiconductor in the light emitting part.Type: ApplicationFiled: August 8, 2014Publication date: November 27, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi Tachibana, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
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Patent number: 8895956Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type first semiconductor layer, a p-type second semiconductor layer and a light emitting layer. The light emitting layer is provided between the first and second semiconductor layers, and includes a plurality of barrier layers including a nitride semiconductor and a well layer provided between the barrier layers and including a nitride semiconductor containing In. The barrier layers and the well layer are stacked in a first direction from the second semiconductor layer toward the first semiconductor layer. The well layer has a p-side interface part and an n-side interface part. Each of the p-side and the n-side interface part include an interface with one of the barrier layers. A variation in a concentration of In in a surface perpendicular to the first direction of the p-side interface part is not more than that of the n-side interface part.Type: GrantFiled: August 26, 2011Date of Patent: November 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shigeya Kimura, Koichi Tachibana, Hajime Nago, Shinya Nunoue
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Publication number: 20140339500Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a p-type layer, and a light emitting unit provided between the n-type layer and the p-type layer and including barrier layers and well layers. At least one of the barrier layers includes first and second portion layers. The first portion layer is disposed on a side of the n-type layer. The second portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the first portion layer. At least one of the well layers includes third and fourth portion layers. The third portion layer is disposed on a side of the n-type layer. The fourth portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the third portion layer.Type: ApplicationFiled: July 30, 2014Publication date: November 20, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshiki HIKOSAKA, Koichi TACHIBANA, Hajime NAGO, Shinya NUNOUE
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Patent number: 8890195Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first, a second and a third conductive layer. The stacked structural body includes first and second semiconductors and a light emitting layer provided therebetween. The second semiconductor layer is disposed between the first conductive layer and the light emitting layer. The first conductive layer is transparent. The first conductive layer has a first major surface on a side opposite to the second semiconductor layer. The second conductive layer is in contact with the first major surface. The third conductive layer is in contact with the first major surface and has a reflectance higher than a reflectance of the second conductive layer. The third conductive layer includes an extending part extending in parallel to the first major surface. At least a portion of the extending part is not covered by the second conductive layer.Type: GrantFiled: January 23, 2013Date of Patent: November 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Taisuke Sato, Toshiyuki Oka, Koichi Tachibana, Shinya Nunoue
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Patent number: 8878213Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a light emitting layer, a p-type layer, and a transparent electrode. The n-type layer includes a nitride semiconductor and has a thickness not more than 500 nm. The light emitting layer is provided on the n-type layer. The p-type layer is provided on the light emitting layer and includes a nitride semiconductor. The transparent electrode contacts the n-type layer. The n-type layer is disposed between the transparent electrode and the light emitting layer.Type: GrantFiled: August 29, 2011Date of Patent: November 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Naoharu Sugiyama, Tomonari Shioda, Shigeya Kimura, Koichi Tachibana, Shinya Nunoue
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Patent number: 8835901Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting part, and a multilayered structural body. The light emitting part is provided between the first and second semiconductor layers and includes barrier layers and well layers alternately stacked. The multilayered structural body is provided between the first semiconductor layer and the light emitting part and includes high energy layers and low energy layers alternately stacked. An average In composition ratio on a side of the second semiconductor is higher than that on a side of the first semiconductor in the multilayered structural body. An average In composition ratio on a side of the second semiconductor is higher than that on a side of the first semiconductor in the light emitting part.Type: GrantFiled: February 18, 2011Date of Patent: September 16, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Tachibana, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
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Patent number: 8835904Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a p-type layer, and a light emitting unit provided between the n-type layer and the p-type layer and including barrier layers and well layers. At least one of the barrier layers includes first and second portion layers. The first portion layer is disposed on a side of the n-type layer. The second portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the first portion layer. At least one of the well layers includes third and fourth portion layers. The third portion layer is disposed on a side of the n-type layer. The fourth portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the third portion layer.Type: GrantFiled: November 27, 2013Date of Patent: September 16, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Koichi Tachibana, Hajime Nago, Shinya Nunoue
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Patent number: 8835950Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.Type: GrantFiled: February 16, 2012Date of Patent: September 16, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
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Publication number: 20140252395Abstract: According to one embodiment, a semiconductor light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, a light emitting layer, a p-side electrode and an n-side electrode. The p-type semiconductor layer includes a nitride semiconductor and has a first major surface. The n-type semiconductor layer includes a nitride semiconductor and has a second major surface. The light emitting layer is provided between the n-type semiconductor layer and the p-type semiconductor layer. The p-side electrode contacts a part of the p-type semiconductor layer on the first major surface. The n-side electrode contacts a part of the n-type semiconductor layer on the second major surface. The n-side electrode is provided outside and around the p-side electrode in a plan view along a direction from the p-type semiconductor layer to the n-type semiconductor layer.Type: ApplicationFiled: May 19, 2014Publication date: September 11, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Taisuke SATO, Shigeya Kimura, Kotaro Zaima, Koichi Tachibana, Shinya Nunoue
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Patent number: 8815717Abstract: According to one embodiment, a vapor deposition method is disclosed for forming a nitride semiconductor layer on a substrate by supplying a group III source-material gas and a group V source-material gas. The method can deposit a first semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of not less than 10 atomic percent by supplying the group III source-material gas from a first outlet and by supplying the group V source-material gas from a second outlet. The method can deposit a second semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of less than 10 atomic percent by mixing the group III and group V source-material gases and supplying the mixed group III and group V source-material gases from at least one of the first outlet and the second outlet.Type: GrantFiled: September 3, 2010Date of Patent: August 26, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiyuki Harada, Koichi Tachibana, Toshiki Hikosaka, Hajime Nago, Shinya Nunoue
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Publication number: 20140209013Abstract: A crystal growth method for nitride semiconductors, including the steps of growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate, with the use of a first carrier gas formed with an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer, with the use of a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer, with the use of a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.Type: ApplicationFiled: April 3, 2014Publication date: July 31, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomonari SHIODA, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
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Publication number: 20140204970Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.Type: ApplicationFiled: March 20, 2014Publication date: July 24, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Koichi TACHIBANA, Chie HONGO, Hajime NAGO, Shinya NUNOUE
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Patent number: 8766311Abstract: According to one embodiment, a semiconductor light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, a light emitting layer, a p-side electrode and an n-side electrode. The p-type semiconductor layer includes a nitride semiconductor and has a first major surface. The n-type semiconductor layer includes a nitride semiconductor and has a second major surface. The light emitting layer is provided between the n-type semiconductor layer and the p-type semiconductor layer. The p-side electrode contacts a part of the p-type semiconductor layer on the first major surface. The n-side electrode contacts a part of the n-type semiconductor layer on the second major surface. The n-side electrode is provided outside and around the p-side electrode in a plan view along a direction from the p-type semiconductor layer to the n-type semiconductor layer.Type: GrantFiled: August 10, 2011Date of Patent: July 1, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Taisuke Sato, Shigeya Kimura, Kotaro Zaima, Koichi Tachibana, Shinya Nunoue
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Publication number: 20140153602Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting part, and a p-side electrode. The light emitting part is provided between the n-type and the p-type semiconductor layers, and includes a plurality of barrier layers and a plurality of well layers. The p-side electrode contacts the p-type semiconductor layer. The p-type semiconductor layer includes first, second, third, and fourth p-type layers. The first p-type layer contacts the p-side electrode. The second p-type layer contacts the light emitting part. The third p-type layer is provided between the first p-type layer and the second p-type layer. The fourth p-type layer is provided between the second p-type layer and the third p-type layer. The second p-type layer contains Al and contains a p-type impurity in a lower concentration lower than that in the first concentration.Type: ApplicationFiled: February 7, 2014Publication date: June 5, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Koichi Tachibana, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
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Patent number: 8741686Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.Type: GrantFiled: March 15, 2013Date of Patent: June 3, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
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Patent number: 8729578Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer and a light emitting layer. The second semiconductor layer is provided on a [0001]-direction side of the first semiconductor layer. The light emitting layer includes a first well layer, a second well layer and a first barrier layer. An In composition ratio of the barrier layer is lower than that of the first well layer and the second well layer. The barrier layer includes a first portion and a second portion. The second portion has a first region and a second region. The first region has a first In composition ratio higher than that of the first portion. The second region is provided between the first region and the first well layer. The second region has a second In composition ratio lower than the first In composition ratio.Type: GrantFiled: March 14, 2013Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shigeya Kimura, Hajime Nago, Koichi Tachibana, Shinya Nunoue
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Patent number: 8728237Abstract: A method for growing nitride semiconductor crystals contains: growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate at a first growth temperature, using a first carrier gas containing an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer at a second growth temperature higher than the first growth temperature, using a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer at the second growth temperature, using a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.Type: GrantFiled: September 2, 2010Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
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Publication number: 20140124735Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting portion. The light emitting portion is provided between the semiconductor layers and includes barrier layers and well layers alternately stacked. An n-side end well layer which is closest to the n-type semiconductor layer contains InwnGa1-wnN and has a layer thickness twn. An n-side end barrier layer which is closest to the n-type semiconductor layer contains InbnGa1-bnN and has a layer thickness tbn. A p-side end well layer which is closest to the p-type semiconductor layer contains InwpGa1-wpN and has a layer thickness twp. A p-side end barrier layer which is closest to the p-type semiconductor contains InbpGa1-bpN and has a layer thickness tbp. A value of (wp×twp+bp×tbp)/(twp+tbp) is higher than (wn×twn+bn×tbn)/(twn+tbn) and is not higher than 5 times (wn×twn+bn×tbn)/(twn+tbn).Type: ApplicationFiled: January 14, 2014Publication date: May 8, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi TACHIBANA, Toshiki Hikosaka, Shigeya Kimura, Hajime Nago, Shinya Nunoue
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Publication number: 20140117309Abstract: According to one embodiment, a crystal growth method is disclosed for growing a crystal of a nitride semiconductor on a major surface of a substrate. The major surface is provided with asperities. The method can include depositing a buffer layer on the major surface at a rate of not more than 0.1 micrometers per hour. The buffer layer includes GaxAl1-xN (0.1?x<0.5) and has a thickness of not smaller than 20 nanometers and not larger than 50 nanometers. In addition, the method can include growing the crystal including a nitride semiconductor on the buffer layer at a temperature higher than a temperature of the substrate in the depositing the buffer layer.Type: ApplicationFiled: January 3, 2014Publication date: May 1, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Hajime NAGO, Koichi TACHIBANA, Toshiki HIKOSAKA, Shinya NUNOUE
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Publication number: 20140109831Abstract: According to one embodiment, a vapor deposition method is disclosed for forming a nitride semiconductor layer on a substrate by supplying a group III source-material gas and a group V source-material gas. The method can deposit a first semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of not less than 10 atomic percent by supplying the group III source-material gas from a first outlet and by supplying the group V source-material gas from a second outlet. The method can deposit a second semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of less than 10 atomic percent by mixing the group III and group V source-material gases and supplying the mixed group III and group V source-material gases from at least one of the first outlet and the second outlet.Type: ApplicationFiled: December 30, 2013Publication date: April 24, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiyuki HARADA, Koichi Tachibana, Toshiki Hikosaka, Hajime Nago, Shinya Nunoue