Patents by Inventor Koji Arai
Koji Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020080640Abstract: There are provided a plurality of memory mats, including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells coupled to the plurality of bit lines, and the plurality of word lines are provided in a direction of the bit line. A sense amplifier array including a plurality of latch circuits is provided in areas between the memory mats arranged in the bit line direction, respectively, and a pair of input/output nodes of which are connected to a pair of bit lines separately placed in the memory mats on both sides of the area, respectively. In this case, for a general memory mat other than both end portions in the bit line direction, word lines in any one of the memory mats are activated, while, for end memory mats provided on both end portions in the bit line direction, word lines of both memory mats are activated together.Type: ApplicationFiled: February 28, 2002Publication date: June 27, 2002Inventors: Hiroki Fujisawa, Riichiro Takemura, Koji Arai
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Publication number: 20020062257Abstract: The present invention relates to a Net shopping method for performing Net shopping through the Internet with a portable terminal. The user freely makes product selections (Net shopping) at any time and place using a portable terminal 2. When the user proposes to conduct a transaction, transaction proposal information, payee information, and the amount of money are automatically sent from the Net shopping site to the portable terminal 2 and stored in the internal memory 22. Next, the user takes the portable terminal 2 to the automatic payment transfer device 4, connects the portable terminal to the payment transfer device 4, and transfers the internal data to the payment transfer device 4. The user can perform payment transfer operations with the payment transfer device 4 based on the order acceptance data. Thus the payment transfer process can be performed safely and with a simple operation.Type: ApplicationFiled: March 23, 2001Publication date: May 23, 2002Inventors: Hayato Minamishin, Tsuyoshi Abe, Koji Arai
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Publication number: 20020059324Abstract: A database update method for a computer system having a host computer and a storage sub-system where a database is maintained is disclosed. The storage sub-system includes first and second storage units containing duplicated data. The host computer accesses the first storage unit for data reading and the second storage unit for data writing. If incomplete processing to read is in process when an access request for data writing occurs, the host computer commands the stop of volume duplication of the first and second storage units and issues a write request. In response to this command, data is stored into only the second storage unit. Upon the completion of both read and write processing, the host computer commands the restart of volume duplication of the first and second control units to reflect the data stored into the second storage unit in the first storage unit.Type: ApplicationFiled: April 2, 2001Publication date: May 16, 2002Inventors: Manabu Kitamura, Koji Arai
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Patent number: 6373776Abstract: There are provided a plurality of memory mats, including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells coupled to the plurality of bit lines, and the plurality of word lines are provided in a direction of the bit line. A sense amplifier array including a plurality of latch circuits is provided in areas between the memory mats arranged in the bit line direction, respectively, and a pair of input/output nodes of which are connected to a pair of bit lines separately placed in the memory mats on both sides of the area, respectively. In this case, for a general memory mat other than both end portions in the bit line direction, word lines in any one of the memory mats are activated, while, for end memory mats provided on both end portions in the bit line direction, word lines of both memory mats are activated together.Type: GrantFiled: March 14, 2001Date of Patent: April 16, 2002Assignees: Hitachi, Ltd., Hitachi ULSI System Co., Ltd.Inventors: Hiroki Fujisawa, Riichiro Takemura, Koji Arai
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Patent number: 6370054Abstract: There are provided a plurality of memory mats, including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells coupled to the plurality of bit lines, and the plurality of word lines are provided in a direction of the bit line. A sense amplifier array including a plurality of latch circuits is provided in areas between the memory mats arranged in the bit line direction, respectively, and a pair of input/output nodes of which are connected to a pair of bit lines separately placed in the memory mats on both sides of the area, respectively. In this case, for a general memory mat other than both end portions in the bit line direction, word lines in any one of the memory mats are activated, while, for end memory mats provided on both end portions in the bit line direction, word lines of both memory mats are activated together.Type: GrantFiled: November 6, 2000Date of Patent: April 9, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroki Fujisawa, Riichiro Takemura, Koji Arai
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Patent number: 6362433Abstract: A flexible printed circuit board that is intended to minimize curling is formed having a first polyimide-resin layer with a conductor pattern formed on one surface thereof and supporting that conductor pattern. A second polyimide-resin is formed on another surface of the conductor pattern and covers and protects the circuit of the conductor pattern. The polyimide-resin layers are chosen so that a difference between a coefficient of linear thermal expansion of the first polyimide-resin layer and the coefficient of linear thermal expansion of the second polyimide-resin layer is 3×10−6/K or smaller.Type: GrantFiled: June 4, 1999Date of Patent: March 26, 2002Assignee: Sony Chemicals CorporationInventors: Satoshi Takahashi, Akira Tsutsumi, Noriaki Kudo, Akihiro Arai, Koji Arai, Koichi Uno, Satoshi Oaku, Osamu Ichihara, Hiromasa Ota
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Publication number: 20020004298Abstract: A material containing, as a main component, an organic silicon compound represented by the following general formula:Type: ApplicationFiled: July 9, 2001Publication date: January 10, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Gaku Sugahara, Nobuo Aoi, Koji Arai, Kazuyuki Sawada
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Publication number: 20010051228Abstract: A material containing, as a main component, an organic silicon compound represented by the following general formula:Type: ApplicationFiled: July 9, 2001Publication date: December 13, 2001Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Gaku Sugahara, Nobuo Aoi, Koji Arai, Kazuyuki Sawada
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Patent number: 6302792Abstract: In a computer role-playing game, the level of an enemy character is set to a proper value in various story developments. When a player character first encounters an enemy character, the level of the enemy character is calculated on the basis of the current level of the player character, and the thus-set level of the enemy character is maintained during the game.Type: GrantFiled: August 18, 1999Date of Patent: October 16, 2001Assignee: Hudson Soft Co., Ltd.Inventors: Koji Arai, Hideki Sahashi
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Publication number: 20010022497Abstract: An EL device comprising a first electrode, an EL layer formed on the first electrode, and a second electrode formed on the EL layer, wherein at least one layer of a material whose wettability changes when light is applied thereto is formed. The invention provides EL devices that can be simply produced, and processes for producing the same.Type: ApplicationFiled: February 22, 2001Publication date: September 20, 2001Applicant: DAI NIPPON PRINTING CO.,Inventors: Daigo Aoki, Masato Okabe, Hironori Kobayashi, Manabu Yamamoto, Tatsuya Miyoshi, Koji Arai, Hiroshi Kishimoto
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Publication number: 20010022659Abstract: This invention discloses an image forming apparatus having an image reading function that can correct the density even when an image is formed based on data acquired from an apparatus other than an image reading apparatus, and a control method therefor. A printer controller (2103) includes a PG unit (3112) for generating a pattern having a predetermined density. The pattern is transmitted to an engine controller (2002) via an output I/F to obtain a print result. Correction data representing the difference between a result obtained by reading the print result and a predetermined characteristic is received from a reader controller via a serial communication controller (3111). The correction data is stored in a data correction unit (3108) and used for printing data subsequently received via an input I/F.Type: ApplicationFiled: March 2, 2001Publication date: September 20, 2001Inventor: Koji Arai
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Publication number: 20010009519Abstract: There is provided memory mats including bit lines, word lines, and memory cells coupled to the bit lines and word lines, and a sense amplifier array including latch circuits provided in areas between the memory mats placed in the bit line direction, respectively, a pair of input/output nodes of which is connected to a pair of bit lines separately placed in the memory mats on both sides of the area, respectively. For a general memory mat other than both end portions in the bit line direction, word lines in any one of the memory mats are activated while, for end memory mats provided on the both end portions in the bit line direction, word lines of the both memory mats are activated together.Type: ApplicationFiled: March 14, 2001Publication date: July 26, 2001Inventors: Hiroki Fujisawa, Riichiro Takemura, Koji Arai
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Patent number: 6254083Abstract: When a driven piece is caused to move forward, a follower piece is allowed to follow the forward movement of the driven piece with the assistance of the biasing force of a biasing member. The follower piece induces the movement of a urging member toward a pickup roller. When the urging member collides against the pickup roller with leaves interposed therebetween, the forward movement of the follower piece is prevented, while the driven piece is still allowed to keep moving forward. The elastic force is stored in the biasing member in response to the forward movement of the driven piece. The urging member is allowed to urge the leaves against the pickup roller by an urging force based on the elastic force stored in the biasing member. When the driven piece is caused to move backward, the follower piece receives the driven piece at the reception surface. The follower piece is allowed to rigidly receive the driving force from the driven piece without any influence of the biasing member.Type: GrantFiled: March 31, 2000Date of Patent: July 3, 2001Assignee: Fujitsu LimitedInventors: Hayami Abe, Yuji Tanaka, Koji Arai
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Patent number: 6233821Abstract: The present invention aims to obtain a flexible printed wiring board with good flatness. According to the present invention, a copper-clad film 3 is formed by applying a polyamic acid solution on one surface of a copper foil 2 and thermally contracting the polyamic acid layer la so that the other surface of the copper foil 2 may form a convex surface of a curling surface to form a polyimide film 1. A polyamic acid solution is applied on the other surface of the copper foil 2 of the copper-clad film 3, and then the polyamic acid layer 5a is thermally contracted to form a protective film 5, whereby a flexible printed wiring board 10 is obtained.Type: GrantFiled: March 15, 1999Date of Patent: May 22, 2001Assignee: Sony Chemicals Corp.Inventors: Satoshi Takahashi, Akira Tsutsumi, Noriaki Kudo, Akihiro Arai, Koji Arai, Koichi Uno, Satoshi Oaku, Osamu Ichihara, Hiromasa Ota
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Patent number: 6184920Abstract: A picture signal transmitting system using a CATV network sends a picture signal from a transmission path to subscribers by using a radio transmitter and receiver, and in the picture signal transmitting system, there is no physical wire connection from a tap off of the transmission path to subscribers.Type: GrantFiled: January 23, 1998Date of Patent: February 6, 2001Assignee: Fujitsu LimitedInventors: Shigefumi Masuda, Hiroyuki Yatsuka, Koji Arai
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Patent number: 6169698Abstract: Drop in the power supply level right after change can be suppressed greatly when changing the power to the internal power supply voltage from the external power supply voltage of an overdrive system. Voltage generating circuit VG0 is connected to the VDL line which raises the VDL line to a voltage higher than VDL beforehand prior to changing to internal power supply voltage VDL from external power supply voltage VDD, and restores the VDL line voltage which drops after the change to VDL.Type: GrantFiled: November 9, 1998Date of Patent: January 2, 2001Assignees: Texas Instruments Incorporated, Hitachi, Ltd.Inventors: Shunichi Sukegawa, Shinji Bessho, Masayuki Hira, Yasushi Takahashi, Tsutomu Takahashi, Koji Arai
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Patent number: 6097648Abstract: An equalizer control line BLEQ shared by all sense amplifiers SA in each row in each submat SM is connected to a first equalizer control line driver consisting of P-type MOS transistors installed at the left end of the submat SM and is connected to several second equalizer control line drivers 32 consisting of N-type MOS transistors installed by dividing in a cross area 16 of each row through which the equalizer control line BLEQ passes. In order to turn on the equalizers of the bit line pair connected to each sense amplifier S, the first equalizer control line driver is operated to drive the equalizer control line BLEQ to the H level potential. In order to turn off the equalizers of each bit line pair, the second equalizer control line drivers 32 are operated to drive the equalizer control line BLEQ to the L level potential. The first and second equalizer control line drivers are complementarily operated. One of them is driven, and the other is turned off (blocked).Type: GrantFiled: April 24, 1998Date of Patent: August 1, 2000Assignees: Texas Instruments Incorporated, Hitachi, Ltd.Inventors: Shinji Bessho, Shunichi Sukegawa, Masayuki Hira, Yasushi Takahashi, Tsutomu Takahashi, Koji Arai
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Patent number: 6049499Abstract: To reduce both the noise level according to separation or short-circuitng of the electrical supply line of the sense amplifiers and the electrical supply line of the word line driving circuit and to effectively prevent destruction of the stored data in the nonselecteded memory cell. Electrical supply line (Vssw) of the power supply voltage with respect to word line driving circuit (SWD) and electrical supply line (Vssa) of power supply voltage with respect to sense amplifier driving circuit (SAD) are arranged separately in memory array area 2 (e.g., in the space in the row direction of memory array (SMAx,y)) and connected to shared electrical supply wiring (Vsso) within peripheral circuit area 3.Type: GrantFiled: July 17, 1998Date of Patent: April 11, 2000Assignees: Texas Instruments Incorporated, Hitachi, Ltd.Inventors: Shunichi Sukegawa, Shinji Bessho, Masayuki Hira, Yasushi Takahashi, Tsutomu Takahashi, Koji Arai
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Patent number: 6023559Abstract: An image processing apparatus includes an engine controller for controlling an image forming mechanism for forming an image on a sheet based on image data, a printer controller for forming image data from printing data transferred from an external apparatus, for transmitting the image data to the engine controller, and for transmitting a command for setting an operation of the engine controller to the engine controller, and a reader controller for controlling an original-reading device for outputting image data by reading an image of an original, and for transmitting the image data output from the original-reading device to the engine controller. The reader controller is provided between the printer controller and the engine controller so as to be in communication with both the printer controller and the engine controller, and so as to control an acquisition right to use the engine controller with the printer controller.Type: GrantFiled: July 29, 1997Date of Patent: February 8, 2000Assignee: Canon Kabushiki KaishaInventors: Hideto Kohtani, Koji Arai, Takashi Nonaka
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Patent number: 6002162Abstract: Realizing a reduction of the layout surface area by rendering unnecessary the region used for well isolation. In this DRAM, a triple well construction is used, and all of the regions for the unit memory cell array MA, the word line driver bank WDB, the sense amplifier bank SAB, and the cross area CR are surrounded by a lower layer N-type deep (deep layer) well 12. A back bias VPP corresponding to the power supply voltage of the word line driver is applied to the N well 14, and a back bias VBB corresponding to the characteristics of the memory cell are applied to the P well 16. In the N well 14, in regard to the P-type MOS transistors of the sense amplifier that undergo the substrate bias effect due to the back bias VPP, the threshold voltage is set to a low value so as to cancel that bias effect.Type: GrantFiled: June 4, 1998Date of Patent: December 14, 1999Assignee: Texas Instruments IncorporatedInventors: Yasushi Takahashi, Tsutomu Takahashi, Koji Arai, Shinji Bessho, Shunichi Sukegawa, Masayuki Hira