Patents by Inventor Koji Araki

Koji Araki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170341629
    Abstract: A drive unit for actuating a brake device by a driver's operation, when a vehicle is parked or stopped, is disposed independently in a trailing arm for each of right and left rear wheels. Thus, the drive unit for actuating the brake device via a wire when the vehicle is stopped or parked can be loaded, even if the space of the vehicle is tight. That is, the drive unit for actuating the brake device via the wire when the vehicle is stopped or parked can be loaded, regardless of the space of the vehicle.
    Type: Application
    Filed: March 29, 2017
    Publication date: November 30, 2017
    Applicants: Mitsubishi Jidosha Kogyo Kabushiki Kaisha, Mitsubishi Jidosha Engineering Kabushiki Kaisha, Hiruta Kogyo Co., Ltd.
    Inventors: Shinji KUROYANAGI, Shinya KAGECHIKA, Hiromitsu TOYOTA, Koji ARAKI, Shunichi OHTSUKI, Yuuya HARUTA
  • Publication number: 20170250137
    Abstract: According to one embodiment, there is provided a semiconductor device including a first wiring, a semiconductor chip, a first bonding member, having a first melting temperature, located between the first wiring and the semiconductor chip, and a second wiring including a first connection unit and a second connection unit spaced from the first connection unit. A second bonding member having a second melting temperature higher than the first melting temperature is located between the semiconductor chip and the first connection unit. A third wiring is also provided, and a third bonding member having a third melting temperature lower than the second melting temperature is located between the second connection unit and the third wiring.
    Type: Application
    Filed: August 31, 2016
    Publication date: August 31, 2017
    Inventors: Koji ARAKI, Satoshi HATTORI
  • Publication number: 20160293446
    Abstract: Provided is a method for manufacturing a silicon wafer including a first step of heat-treating a raw silicon wafer sliced from a silicon single crystal ingot grown by the Czochralski method in an oxidizing gas atmosphere at a maximum target temperature of 1300 to 1380° C., a second step of removing an oxide film on a surface of the heated-treated silicon wafer obtained in the first step, and a third step of heat-treating the stripped silicon wafer obtained in the second step in a non-oxidizing gas atmosphere at a maximum target temperature of 1200 to 1380° C. and at a heating rate of 1° C./sec to 150° C./sec in order that the silicon wafer may have a maximum oxygen concentration of 1.3×1018 atoms/cm3 or below in a region from the surface up to 7 ?m in depth.
    Type: Application
    Filed: March 28, 2016
    Publication date: October 6, 2016
    Applicant: GlobalWafers Japan Co., Ltd.
    Inventors: Haruo SUDO, Koji ARAKI, Tatsuhiko AOKI, Susumu MAEDA
  • Patent number: 9059099
    Abstract: There is provided a thermal treatment method of a silicon wafer. The method includes the successive steps of: (a) terminating silicon atoms existing on an active surface of the silicon wafer with hydrogen, wherein the active surface is mirror-polished, and a semiconductor device is to be formed on the active surface; (b) terminating the silicon atoms existing on the active surface of the silicon wafer with fluorine; (c) rapidly heating the silicon wafer to a first temperature under an inert gas atmosphere or a reducing gas atmosphere, wherein the first temperature is in a range of 1300° C. to 1400° C.; (d) holding the silicon wafer at the first temperature for a certain time; and (e) rapidly cooling the silicon wafer.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: June 16, 2015
    Assignee: GLOBAL WAFERS JAPAN CO., LTD.
    Inventors: Takeshi Senda, Koji Araki
  • Patent number: 8999864
    Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: April 7, 2015
    Assignee: Global Wafers Japan Co., Ltd.
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
  • Publication number: 20150069593
    Abstract: In one embodiment, a semiconductor device includes a lead frame including a chip mounting portion and a lead portion separated from the chip mounting portion and having the same thickness as the chip mounting portion, a level of an upper face of the chip mounting portion being same as a level of an upper face of the lead portion. The device further includes a semiconductor chip mounted on the upper face of the chip mounting portion and electrically connected to the lead portion. The device further includes a molding resin which collectively seals up the lead frame and the semiconductor chip. The device further includes a metal film covering parts of rear faces of the chip mounting portion and the lead portion.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinichi Koyama, Koji Araki, Tatsuo Tonedachi, Kazumi Otani
  • Publication number: 20150044422
    Abstract: A silicon wafer is manufactured by subjecting a silicon wafer sliced from a silicon single-crystal ingot grown by the Czochralski process to a rapid thermal process in which the silicon wafer is heated to a maximum temperature within a range of 1300 to 1380° C., and kept at the maximum temperature for 5 to 60 seconds; and removing a surface layer of the wafer where a semiconductor device is to be manufactured by a thickness of not less X [?m] which is calculated according to the below equations (1) to (3): X[?m]=a[?m]+b[?m]??(1); a[?m]=(0.0031×(said maximum temperature)[° C.]?3.1)×6.4×(cooling rate)?0.4[° C./second] . . . (2); and b[?m]=a/(solid solubility limit of oxygen) [atoms/cm3]/(oxygen concentration in substrate) [atoms/cm3]??(3).
    Type: Application
    Filed: July 31, 2014
    Publication date: February 12, 2015
    Inventors: Koji ARAKI, Tatsuhiko AOKI, Haruo SUDO, Takeshi SENDA
  • Patent number: 8476149
    Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: July 2, 2013
    Assignee: Global Wafers Japan Co., Ltd.
    Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Yoichiro Mochizuki, Akihiko Kobayashi, Senlin Fu
  • Publication number: 20130078588
    Abstract: A method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD density along a diameter of a bulk of the wafer grown by the CZ process can be improved. Further, a method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD size can also be improved and COP of a surface layer of the wafer can be reduced. The method includes a step of a first heat treatment in which the CZ silicon wafer is heated to a temperature from 1325 to 1400° C. in an oxidizing gas atmosphere, held at the temperature, and then cooled at a cooling rate of from 50 to 250° C./second, and a step of a second heat treatment in which the wafer is heated to a temperature from 900 to 1200° C. in a non-oxidizing gas atmosphere, held at the temperature, and then cooled.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 28, 2013
    Applicant: Covalent Silicon Corporation
    Inventors: Takeshi Senda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Susumu Maeda
  • Patent number: 8399341
    Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: March 19, 2013
    Assignee: Covalent Materials Corporation
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
  • Publication number: 20120241912
    Abstract: There is provided a thermal treatment method of a silicon wafer. The method includes the successive steps of: (a) terminating silicon atoms existing on an active surface of the silicon wafer with hydrogen, wherein the active surface is mirror-polished, and a semiconductor device is to be formed on the active surface; (b) terminating the silicon atoms existing on the active surface of the silicon wafer with fluorine; (c) rapidly heating the silicon wafer to a first temperature under an inert gas atmosphere or a reducing gas atmosphere, wherein the first temperature is in a range of 1300° C. to 1400° C.; (d) holding the silicon wafer at the first temperature for a certain time; and (e) rapidly cooling the silicon wafer.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 27, 2012
    Applicant: Covalent Materials Corporation
    Inventors: Takeshi SENDA, Koji Araki
  • Patent number: 8252700
    Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: August 28, 2012
    Assignee: Covalent Materials Corporation
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
  • Publication number: 20120184091
    Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.
    Type: Application
    Filed: May 17, 2010
    Publication date: July 19, 2012
    Applicant: Covalent Materials Corporation
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
  • Publication number: 20120139088
    Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.
    Type: Application
    Filed: May 28, 2010
    Publication date: June 7, 2012
    Applicant: Covalent Materials Corporation
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
  • Publication number: 20110023413
    Abstract: A packaging apparatus includes a conveying unit that conveys a continuous film in a first direction with an article placed on a first portion of the film, and folds back in a second direction opposite to the first direction a second portion of the film ahead of the first portion with respect to the first direction, sealing parts that seal the first portion and the second portion to form a bag body containing the article, and a cutter that cuts the film.
    Type: Application
    Filed: July 26, 2010
    Publication date: February 3, 2011
    Applicant: ISHIDA CO., LTD.
    Inventors: Akihito SUZUKI, Ryoichi KAWAMURA, Yuuki TAI, Koji ARAKI, Tsuyoshi ONO, Tetsuya TSUDA
  • Publication number: 20100197146
    Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.
    Type: Application
    Filed: January 21, 2010
    Publication date: August 5, 2010
    Applicant: COVALENT MATERIALS CORPORATION
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
  • Publication number: 20100038757
    Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 18, 2010
    Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Yoichiro Mochizuki, Akihiko Kobayashi, Senlin Fu
  • Publication number: 20080237190
    Abstract: A surface cleaning method of a semiconductor wafer heat treatment boat that can prevent metallic contamination to semiconductor wafers and keep down a production time and manufacturing costs of semiconductor wafers by efficiently and easily removing metallic impurities in an oxide film on an SiC boat surface is provided. A surface cleaning method of a semiconductor wafer heat treatment boat according to an embodiment of the present invention is a surface cleaning method of a semiconductor wafer heat treatment boat whose surface is formed of SiC, includes oxidizing the surface of the heat treatment boat by thermal oxidation and etching a portion of the oxide film formed after oxidation is removed.
    Type: Application
    Filed: September 26, 2007
    Publication date: October 2, 2008
    Applicant: Covalent Materials Corporation
    Inventors: Tatsuhiko Aoki, Motohiro Sei, Koji Araki
  • Patent number: 7412821
    Abstract: An engine ECU executes a program including the step of performing an operation for rapid catalyst warm-up, under the conditions that an engine is started and rapid catalyst warm-up is necessary, by setting the ratio of fuel injection by an in-cylinder injector to be equal to or higher than that of an intake manifold injector and retarding the ignition timing to a large degree, and the step of performing normal operation under the condition that the catalyst is warmed up to be activated.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: August 19, 2008
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Koji Araki, Yoshiyuki Shogenji
  • Publication number: 20080166891
    Abstract: The present invention provides a heat treatment method for a silicon wafer in which, with respect to a surface of the silicon wafer made flat at an atomic level by a high-temperature heat-treatment at 1,100° C. or more, a surface roughness of the wafer can be reduced compared with the conventional one while maintaining a step terrace structure on the surface of the above-mentioned wafer, and the surface of such a wafer can be formed stably. In the heat treatment method for the silicon wafer in which the step terrace structure is formed on the surface of the silicon wafer, after the silicon wafer is heat treated at 1,100° C. or more in a heat treatment furnace in a reducing gas or inert gas atmosphere, the atmosphere in the furnace is arranged to be of argon gas at a temperature of 500° C.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 10, 2008
    Inventors: Manabu Hirasawa, Koji Izunome, Koji Araki, Tatsuhiko Aoki