Patents by Inventor Koji Kamei

Koji Kamei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961736
    Abstract: A SiC epitaxial wafer in which a SiC epitaxial layer is formed on a 4H-SiC single crystal substrate having an off angle and a substrate carbon inclusion density of 0.1 to 6.0 inclusions/cm2, wherein a total density of large pit defects and triangular defects caused by substrate carbon inclusions and contained in the SiC epitaxial layer is 0.01 defects/cm2 or more and 0.6 defects/cm2 or less. The large pit defect is a pit located on a surface at a position corresponding to a position of the carbon inclusion on the substrate surface, and a conversion rate from the substrate carbon inclusions to the large pit defects and the triangular defects caused by the substrate carbon inclusions is 20% or less. Also disclosed is a method for producing the SiC epitaxial wafer.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 16, 2024
    Assignee: Resonac Corporation
    Inventors: Ling Guo, Koji Kamei
  • Patent number: 11938852
    Abstract: A sensor disposition structure in a seat includes a cushion pad and a board-like member which is disposed under the cushion pad. A concave is formed in an upper surface of the board-like member, and a sensor is disposed in the concave.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: March 26, 2024
    Assignee: TS TECH CO., LTD.
    Inventors: Soichiro Kamei, Hiromi Taniguchi, Koji Onuma
  • Publication number: 20230392288
    Abstract: A SiC single crystal substrate of an embodiment has a diameter being 199 mm or more, wherein the density of threading dislocations per area of 0.25 mm2 arbitrarily selected in the main surface of the SiC single crystal substrate is 5×104/cm2 or less, and the threading dislocations include a threading edge dislocation.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 7, 2023
    Applicant: Resonac Corporation
    Inventors: Takuya YAMAGUCHI, Koji Kamei, Naoki Oyanagi
  • Publication number: 20230268177
    Abstract: According to the present invention, there is provided a SiC epitaxial wafer including: a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 ?m or more, which is formed on the 4H-SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Applicant: SHOWA DENKO K.K.
    Inventor: Koji KAMEI
  • Patent number: 11705329
    Abstract: According to the present invention, there is provided a SiC epitaxial wafer including: a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 ?m or more, which is formed on the 4H-SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: July 18, 2023
    Assignee: SHOWA DENKO K.K.
    Inventor: Koji Kamei
  • Publication number: 20220259764
    Abstract: A SiC epitaxial wafer in which a SiC epitaxial layer is formed on a 4H—SiC single crystal substrate having an off angle and a substrate carbon inclusion density of 0.1 to 6.0 inclusions/cm2, wherein a total density of large pit defects and triangular defects caused by substrate carbon inclusions and contained in the SiC epitaxial layer is 0.01 defects/cm2 or more and 0.6 defects/cm2 or less. The large pit defect is a pit located on a surface at a position corresponding to a position of the carbon inclusion on the substrate surface, and a conversion rate from the substrate carbon inclusions to the large pit defects and the triangular defects caused by the substrate carbon inclusions is 20% or less. Also disclosed is a method for producing the SiC epitaxial wafer.
    Type: Application
    Filed: February 28, 2022
    Publication date: August 18, 2022
    Applicant: SHOWA DENKO K.K.
    Inventors: Ling GUO, Koji KAMEI
  • Publication number: 20220223482
    Abstract: A SiC epitaxial wafer including a high-concentration epitaxial layer having an impurity concentration of 1×1018 cm?3 or more, and the number or positions of basal plane dislocations included in the high-concentration epitaxial layer have been identified
    Type: Application
    Filed: March 29, 2022
    Publication date: July 14, 2022
    Applicant: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Koji Kamei
  • Patent number: 11320388
    Abstract: A SiC epitaxial wafer in which a SiC epitaxial layer is formed on a 4H—SiC single crystal substrate having an off angle and a substrate carbon inclusion density of 0.1 to 6.0 inclusions/cm2, and wherein a density of large pit defects caused by substrate carbon inclusions and contained in the SiC epitaxial layer is 0.5 defects/cm2 or less.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: May 3, 2022
    Assignee: SHOWA DENKO K.K.
    Inventors: Ling Guo, Koji Kamei
  • Patent number: 11315839
    Abstract: An evaluation method of a SiC epitaxial wafer includes: a first observation step of preparing a SiC epitaxial wafer having a high-concentration epitaxial layer having an impurity concentration of 1×1018 cm?3 or more, irradiating a surface of the high-concentration epitaxial layer having an impurity concentration of 1×1018 cm?3 or more with excitation light, and observing a surface irradiated with the excitation light via a band-pass filter having a wavelength band of 430 nm or less.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 26, 2022
    Assignee: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Koji Kamei
  • Patent number: 11293115
    Abstract: A SiC epitaxial wafer in which a SiC epitaxial layer is formed on a 4H-SiC single crystal substrate having an off angle and a substrate carbon inclusion density of 0.1 to 2.5 inclusions/cm2, wherein a total density of large pit defects and triangular defects caused by substrate carbon inclusions and contained in the SiC epitaxial layer is 0.6 defects/cm2 or less.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: April 5, 2022
    Assignee: SHOWA DENKO K.K.
    Inventors: Ling Guo, Koji Kamei
  • Patent number: 11249027
    Abstract: A SiC epitaxial wafer, including: a SiC substrate; and an epitaxial layer stacked on a first surface of the SiC substrate, wherein an area occupied by bar-shaped stacking faults on the first surface of the SiC substrate is identified, and the area occupied by bar-shaped stacking faults on the first surface of the SiC substrate is equal to or less than ¼ of the first surface area of the SiC substrate.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: February 15, 2022
    Assignee: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Koji Kamei
  • Patent number: 10985042
    Abstract: A SiC substrate includes a first principal surface, a second principal surface disposed on a side opposite to the first principal surface, and an outer periphery connected to the first principal surface and the second principal surface, wherein a density of composite defects present at a peripheral edge portion of the SiC substrate, in which a hollow portion and a dislocation line extending from the hollow portion are connected to each other is equal to or greater than 0.01 pieces/cm2 and equal to or less than 10 pieces/cm2.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: April 20, 2021
    Assignee: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Koji Kamei
  • Patent number: 10955350
    Abstract: A SiC wafer defect measuring method which includes a device management step of managing a defect measuring device by irradiating a reference sample made of a material having a light-emitting intensity that does not change with repeated irradiation by excitation light and which has a pattern made of recesses and/or protrusions in the surface, the irradiation by the excitation light being performed before measuring defects in a SiC wafer and under the same irradiation conditions as the measurement of the defects in the SiC wafer, and then measuring the S/N ratio of the pattern from a reflection image of the pattern.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: March 23, 2021
    Assignee: SHOWA DENKO K.K.
    Inventor: Koji Kamei
  • Patent number: 10865500
    Abstract: A SiC epitaxial wafer having a SiC epitaxial layer formed on a SiC single crystal substrate having an offset angle of 4 degrees or less in a<11-20>direction from a (0001) plane. A trapezoidal defect included in the SiC epitaxial wafer includes an inverted trapezoidal defect in which a length of a lower base on a downstream side of a step flow is equal to or less than a length of an upper base on an upstream side of the step flow. Also disclosed is a method for manufacturing the SiC epitaxial wafer.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: December 15, 2020
    Assignee: SHOWA DENKO K.K.
    Inventors: Jun Norimatsu, Akira Miyasaka, Yoshiaki Kageshima, Koji Kamei, Daisuke Muto
  • Publication number: 20200284732
    Abstract: A SiC epitaxial wafer, including: a SiC substrate; and an epitaxial layer stacked on a first surface of the SiC substrate, wherein an area occupied by bar-shaped stacking faults on the first surface of the SiC substrate is identified, and the area occupied by bar-shaped stacking faults on the first surface of the SiC substrate is equal to or less than ¼ of the first surface area of the SiC substrate.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Applicant: SHOWA DENKO K.K.
    Inventors: Yoshitaka NISHIHARA, Koji KAMEI
  • Patent number: 10697898
    Abstract: In a SiC substrate evaluation method, a bar-shaped stacking fault is observed by irradiating a surface of a SiC substrate before stacking an epitaxial layer with excitation light and extracting light having a wavelength range from equal to or greater than 405 nm and equal to or less than 445 nm among photoluminescence light beams emitted from the first surface.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: June 30, 2020
    Assignee: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Koji Kamei
  • Publication number: 20200203163
    Abstract: According to the present invention, there is provided a SiC epitaxial wafer including: a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 ?m or more, which is formed on the 4H-SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.
    Type: Application
    Filed: May 14, 2018
    Publication date: June 25, 2020
    Applicant: SHOWA DENKO K.K.
    Inventor: Koji KAMEI
  • Publication number: 20200116649
    Abstract: In a SiC substrate evaluation method, a bar-shaped stacking fault is observed by irradiating a surface of a SiC substrate before stacking an epitaxial layer with excitation light and extracting light having a wavelength range from equal to or greater than 405 nm and equal to or less than 445 nm among photoluminescence light beams emitted from the first surface.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 16, 2020
    Applicant: SHOWA DENKO K.K.
    Inventors: Yoshitaka NISHIHARA, Koji KAMEI
  • Publication number: 20200118854
    Abstract: A SIC substrate includes a first principal surface, a second principal surface disposed on a side opposite to the first principal surface, and an outer periphery connected to the first principal surface and the second principal surface, wherein a density of composite defects present at a peripheral edge portion of the SIC substrate, in which a hollow portion and a dislocation line extending from the hollow portion are connected to each other is equal to or greater than 0.01 pieces/cm2 and equal to or less than 10 pieces/cm2.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 16, 2020
    Applicant: SHOWA DENKO K.K.
    Inventors: Yoshitaka NISHIHARA, Koji KAMEI
  • Publication number: 20190331603
    Abstract: A SiC wafer defect measuring method which includes a device management step of managing a defect measuring device by irradiating a reference sample made of a material having a light-emitting intensity that does not change with repeated irradiation by excitation light and which has a pattern made of recesses and/or protrusions in the surface, the irradiation by the excitation light being performed before measuring defects in a SiC wafer and under the same irradiation conditions as the measurement of the defects in the SiC wafer, and then measuring the S/N ratio of the pattern from a reflection image of the pattern.
    Type: Application
    Filed: December 7, 2017
    Publication date: October 31, 2019
    Applicant: SHOWA DENKO K.K.
    Inventor: Koji KAMEI