Patents by Inventor Koji Kawakita

Koji Kawakita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160351481
    Abstract: An electronic component package according to one aspect of the present disclosure includes a metal pattern layer having a first principal surface and a second principal surface, an electronic component disposed on the first principal surface and electrically connected to the metal pattern layer, at least one metal member disposed on the first principal surface and electrically connected to the metal pattern layer, a sealing resin layer disposed on the first principal surface, the electronic component and the at least one metal member, and an insulating layer disposed on the second principal surface. The at least one metal member is thicker than the electronic component. In plan view, the at least one metal member is disposed on an area of the first principal surface, the area including an end of the first principal surface. The at least a part of the metal pattern layer is exposed from the insulating layer.
    Type: Application
    Filed: May 18, 2016
    Publication date: December 1, 2016
    Inventors: KOJI KAWAKITA, TAKASHI ICHIRYU, MASANORI NOMURA
  • Publication number: 20160353567
    Abstract: A stretchable flexible substrate according to one aspect of the present disclosure includes: an electronic component; a first insulating layer located around the electronic component and having first and second main surfaces facing each other; a first metal layer that is in contact with the first main surface; a second metal layer that is in contact with the second main surface and electrically connected to the electronic component; and a second insulating layer that seals the electronic component, first insulating layer, and second metal layer, in plan view, a curved wiring portion extending from a central portion made up of at least the electronic component, portions of the first insulating layer and first and second metal layers, the curved wiring portion being made up of at least other portions of the first insulating layer, first and second metal layers, and the curved wiring portion being curved at least partially.
    Type: Application
    Filed: May 19, 2016
    Publication date: December 1, 2016
    Inventors: TAKASHI ICHIRYU, KOJI KAWAKITA, MASANORI NOMURA, YOSHIHIRO TOMITA
  • Patent number: 9449944
    Abstract: There is provided a method for manufacturing an electronic component package, wherein a first electronic component and a second electronic component are placed on a carrier, and a sealing resin layer is formed on the carrier, followed by the carrier being peeled away to be removed, and thereby providing a package precursor in which the first and second electronic components are embedded such that an electrode of at least one of the first and second electronic components is exposed at a surface of the sealing resin layer. Upon the placing of the first and second electronic components, the first and second electronic components are positioned such that their height levels differ from each other. After the removal of the carrier, a metal plating layer is formed such that the metal plating layer is in contact with the exposed surface of the electrode of the at least one of the first and second electronic components.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: September 20, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Susumu Sawada, Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita
  • Patent number: 9449937
    Abstract: There is provided a semiconductor device. The semiconductor device of the present invention includes a semiconductor element and a metal buffer layer in an electrical connection to the semiconductor element. The metal buffer layer and the semiconductor element are in a connection with each other by mutual surface contact of the metal buffer layer and the semiconductor element. The metal buffer layer is an external connection terminal used for a mounting with respect to a secondary mount substrate, and the metal buffer layer serves as a buffer part having a stress-relaxation effect between the semiconductor element and the secondary mount substrate.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: September 20, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Koji Kawakita, Susumu Sawada, Seiichi Nakatani, Yoshihisa Yamashita
  • Patent number: 9425122
    Abstract: A method for manufacturing an electronic component packages is provided, wherein a package precursor is provided, in which an electronic component is embedded in a sealing resin layer such that an electrode of the electronic component is exposed at a surface of the sealing resin layer. A combination of a formation process of a plurality of metal plating layers and a patterning process of the plurality of metal plating layers is provided to form a step-like metal plating layer, the formation process being performed by sequential dry and wet plating processes with respect to the package precursor, and the patterning process being performed by a patterning of at least two of the plurality of metal plating layers.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 23, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Koji Kawakita, Seiichi Nakatani, Susumu Sawada, Yoshihisa Yamashita
  • Patent number: 9373762
    Abstract: An electronic part package comprises a sealing resin layer, an electronic part and a metal plating pattern layer. The sealing resin layer is provided with a principal surface including a first region that has a bellows-like shape having alternate ridges and valleys and a second region that is flat. The electronic part includes an electrode having a principal surface and is covered by the sealing resin layer except the principal surface, which is surrounded by the second region. The metal plating pattern layer is integrally provided on the first and second regions and on the principal surface of the electrode. A portion of the metal plating pattern layer, the portion located on the first region, has a bellows-like shape having alternate ridges and valleys along an outline of the first region.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: June 21, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Susumu Sawada, Yoshihiro Tomita, Koji Kawakita, Masanori Nomura
  • Patent number: 9368469
    Abstract: There is provided a method for manufacturing an electronic component package. The method includes the steps: (i) disposing a metal pattern layer on an adhesive carrier; (ii) placing at least one kind of electronic component on the adhesive carrier, the placed electronic component being not overlapped with respect to the metal pattern layer; (iii) forming a sealing resin layer on the adhesive carrier, and thereby producing a precursor of the electronic component package; (iv) peeling off the adhesive carrier of the precursor, whereby the metal pattern layer and an electrode of the electronic component are exposed at the surface of the sealing resin layer; and (v) forming a metal plating layer such that the metal plating layer is in contact with the exposed surface of the metal pattern layer and the exposed surface of the electrode of the electronic component.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: June 14, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita, Susumu Sawada
  • Patent number: 9236338
    Abstract: A method for manufacturing a build-up substrate, the build-up substrate comprising an insulating layer and a wiring pattern layer stacked over a circuit substrate, said method comprising the steps of: (i) applying a photoactive metal oxide precursor material to one or both sides of the circuit substrate with a wiring pattern, and drying the applied photoactive metal oxide precursor material to form an insulating film; (ii) forming an opening for a via hole in the insulating film by exposure and development of the insulating film; (iii) applying a heat treatment to the insulating film to convert the insulating film into a metal oxide film, thereby forming a build-up insulating layer of the metal oxide film; and (iv) plating the build-up insulating layer to form via holes in the openings, forming a metal layer on the build-up insulating layer, and etching the metal layer to form a build-up wiring pattern; and (v) repeating the steps from (i) to (iv) at least one time.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: January 12, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Seiichi Nakatani, Koji Kawakita, Susumu Sawada, Yoshihisa Yamashita
  • Publication number: 20150364661
    Abstract: An electronic part package comprises a sealing resin layer, an electronic part and a metal plating pattern layer. The sealing resin layer is provided with a principal surface including a first region that has a bellows-like shape having alternate ridges and valleys and a second region that is flat. The electronic part includes an electrode having a principal surface and is covered by the sealing resin layer except the principal surface, which is surrounded by the second region. The metal plating pattern layer is integrally provided on the first and second regions and on the principal surface of the electrode. A portion of the metal plating pattern layer, the portion located on the first region, has a bellows-like shape having alternate ridges and valleys along an outline of the first region.
    Type: Application
    Filed: June 3, 2015
    Publication date: December 17, 2015
    Inventors: SUSUMU SAWADA, YOSHIHIRO TOMITA, KOJI KAWAKITA, MASANORI NOMURA
  • Publication number: 20150280093
    Abstract: There is provided a light-emitting device comprising a light-emitting element, an element electrode, an extending-wiring electrode and a support. In the light-emitting device of the present invention, the light-emitting element is supported and secured by the support in such a form that a principal surface of the support and an active surface of the light-emitting element are approximately flush with each other. Further, the extending-wiring electrode is in a surface contact with the element electrode such that the extending-wiring electrode extends beyond a periphery of the light-emitting element to the principal surface of the support, wholly covering the active surface of the light-emitting element.
    Type: Application
    Filed: August 2, 2013
    Publication date: October 1, 2015
    Inventors: Yoshihiro Tomita, Susumu Sawada, Seiichi Nakatani, Koji Kawakita, Yoshihisa Yamashita
  • Publication number: 20150236233
    Abstract: A method for manufacturing an electronic component package comprises: (i) preparing a metal foil having opposed principal surface “A” for placement of an electronic component and principal surface “B”, and a through-hole located in an electronic component-placement region of the principal surface “A”; (ii) placing the electronic component on the metal foil such that the electronic component is positioned in the electronic component-placement region, and an opening of the through-hole is capped with an electrode of the electronic component; (iii) forming a sealing resin layer on the principal surface “A” such that the electronic component is covered with the sealing resin layer; and (iv) forming a metal plating layer on the principal surface “B”. A dry plating process and a subsequent wet plating process are performed to form the metal plating layer in the (iv) such that the through-hole is filled with the metal plating layer, and the metal foil and the metal plating layer are integrated with each other.
    Type: Application
    Filed: December 20, 2013
    Publication date: August 20, 2015
    Inventors: Yoshihisa Yamashita, Seiichi Nakatani, Koji Kawakita, Susumu Sawada
  • Publication number: 20150228619
    Abstract: There is provided a method for manufacturing an electronic component package, wherein a first electronic component and a second electronic component are placed on a carrier, and a sealing resin layer is formed on the carrier, followed by the carrier being peeled away to be removed, and thereby providing a package precursor in which the first and second electronic components are embedded such that an electrode of at least one of the first and second electronic components is exposed at a surface of the sealing resin layer. Upon the placing of the first and second electronic components, the first and second electronic components are positioned such that their height levels differ from each other. After the removal of the carrier, a metal plating layer is formed such that the metal plating layer is in contact with the exposed surface of the electrode of the at least one of the first and second electronic components.
    Type: Application
    Filed: December 20, 2013
    Publication date: August 13, 2015
    Inventors: Susumu Sawada, Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita
  • Patent number: 9107306
    Abstract: A hybrid substrate includes a core layer composed of a glass woven cloth as a reinforcing material, and a glass-ceramic sintered body which at least has a glass component and a metal oxide component. The glass woven cloth and the glass-ceramic sintered body formed by an impregnation with respect to the glass woven cloth are in a form of sintering integration with each other.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: August 11, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Seiichi Nakatani, Koji Kawakita
  • Publication number: 20150221842
    Abstract: There is provided a method for manufacturing an electronic component package. The method includes (i) providing a package precursor in which an electronic component is embedded such that an electrode of the electronic component is exposed at a surface of a sealing resin layer; (ii) forming a first metal plating layer such that the first metal plating layer is in contact with the exposed surface of the electrode of the electronic component; (iii) disposing a metal foil in face-to-face spaced relationship with respect to the first metal plating layer; and (iv) forming a second metal plating layer, wherein in the step (iv), the second metal plating layer is formed to fill a clearance between the first metal plating layer and the metal foil with the second metal plating layer, and thereby integrating the metal foil, the first metal plating layer and the second metal plating layer with each other.
    Type: Application
    Filed: December 20, 2013
    Publication date: August 6, 2015
    Applicant: Panasonic Intellectual Property Management Co., Lt
    Inventors: Kazuma Mima, Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita, Susumu Sawada
  • Publication number: 20150214129
    Abstract: There is provided a method for manufacturing an electronic component package, wherein a package precursor is provided, in which an electronic component is embedded in a sealing resin layer such that an electrode of the electronic component is exposed at a surface of the sealing resin layer. In the manufacturing method of the present invention, a combination of a formation process of a plurality of metal plating layers and a patterning process of the metal plating layers is provided to form a step-like metal plating layer, the formation process being performed by sequential dry and wet plating processes with respect to the package precursor, the patterning process being performed by a patterning of at least two of the metal plating layers.
    Type: Application
    Filed: December 20, 2013
    Publication date: July 30, 2015
    Inventors: Koji Kawakita, Seiichi Nakatani, Susumu Sawada, Yoshihisa Yamashita
  • Publication number: 20150155251
    Abstract: There is provided a semiconductor device. The semiconductor device of the present invention includes a semiconductor element and a metal buffer layer in an electrical connection to the semiconductor element. The metal buffer layer and the semiconductor element are in a connection with each other by mutual surface contact of the metal buffer layer and the semiconductor element. The metal buffer layer is an external connection terminal used for a mounting with respect to a secondary mount substrate, and the metal buffer layer serves as a buffer part having a stress-relaxation effect between the semiconductor element and the secondary mount substrate.
    Type: Application
    Filed: August 2, 2013
    Publication date: June 4, 2015
    Inventors: Koji Kawakita, Susumu Sawada, Seiichi Nakatani, Yoshihisa Yamashita
  • Publication number: 20150102806
    Abstract: To reduce an indication error at a peripheral part of an electromagnetic induction type coordinate detection device, sensor coils having a coil width of 21 pitches are arranged at a central part at intervals of 4 pitches. At a peripheral part, the coil width is shortened from sensor coil #5 to coil #1 sequentially so that the coil width of a sensor coil is shorter than a coil width of an inwardly adjacent sensor coil by 2 pitches. This enables the coil side pitch that is 1 all over the coil group 222, and an area enabling three-point supplementing can be enlarged from the conventional one. The sensor coils at the peripheral part have a coil pitch of 3, and so an indication error there can be reduced compared with the conventional case of coil pitch of 4 for two-point supplementing as well. Dummy wires required at the peripheral part conventionally can be eliminated.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 16, 2015
    Inventors: Moriyuki Tsuchihashi, Koji Kawakita, Yi Zheng, Kazuo Fujii
  • Publication number: 20150084080
    Abstract: There is provided a light-emitting device comprising a light-emitting element and a substrate for light-emitting element. The light-emitting element is in a mounted state on a mounting surface of the substrate, the mounting surface being one of two opposed main surfaces of the substrate. The substrate is provided with a protection element for the light-emitting element, the protection element comprising a voltage-dependent resistive layer embedded in the substrate, and comprising a first electrode and a second electrode each of which is in connection with the voltage-dependent resistive layer. The mounted light-emitting element is in an overlapping relation with the voltage-dependent resistive layer. A reflective layer is provided on at least one of the substrate and the voltage-dependent resistive layer such that the reflective layer is located adjacent to the first electrode which is in contact with a substrate exposure surface of the voltage-dependent resistive layer.
    Type: Application
    Filed: February 14, 2013
    Publication date: March 26, 2015
    Inventors: Koji Kawakita, Seiichi Nakatani, Tatsuo Ogawa, Susumu Sawada
  • Publication number: 20150076545
    Abstract: There is provided a method for manufacturing an electronic component package. The method includes the steps: (i) disposing a metal pattern layer on an adhesive carrier; (ii) placing at least one kind of electronic component on the adhesive carrier, the placed electronic component being not overlapped with respect to the metal pattern layer; (iii) forming a sealing resin layer on the adhesive carrier, and thereby producing a precursor of the electronic component package; (iv) peeling off the adhesive carrier of the precursor, whereby the metal pattern layer and an electrode of the electronic component are exposed at the surface of the sealing resin layer; and (v) forming a metal plating layer such that the metal plating layer is in contact with the exposed surface of the metal pattern layer and the exposed surface of the electrode of the electronic component.
    Type: Application
    Filed: August 2, 2013
    Publication date: March 19, 2015
    Applicant: Panasonic Intellectual Property Management Co., Lt
    Inventors: Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita, Susumu Sawada
  • Publication number: 20150008467
    Abstract: There is provided a light-emitting device comprising a light-emitting element. The light-emitting device of the present invention comprises an electrode part for the light-emitting element; a reflective layer provided on the electrode part; and the light-emitting element provided on the reflective layer such that the light-emitting element is in contact with at least a part of the reflective layer, wherein the light-emitting element and the electrode part are in an electrical connection with each other by mutual surface contact via the at least a part of the reflective layer, wherein the electrode part serves as a supporting layer for supporting the light-emitting element, and wherein the electrode part extends toward the outside of the light-emitting element and beyond the light-emitting element.
    Type: Application
    Filed: January 28, 2013
    Publication date: January 8, 2015
    Inventors: Susumu Sawada, Seiichi Nakatani, Koji Kawakita, Yoshihisa Yamashita