Abstract: A multiprocessor system includes a master processor, at least one slave processor, and a synchronization unit. The master processor has a first flag indicating whether the master processor is in a task activation accepting state and a second flag reflective of a flag of a slave processor, iteratively updates the first flag at a frequency based on the volume of tasks processed by the master processor, and activates a task on the master processor or the slave processor based on the first flag and the second flag. Each slave processor has a third flag indicating whether the slave processor is in the task activation accepting state and iteratively updates the third flag at a frequency based on the volume of tasks processed by the slave processor. Tasks are allocated to the slave processor by the master processor. The synchronization unit synchronizes the third flag and the second flag.

Abstract: A scheduling method of a scheduler that manages threads is executed by a computer. The scheduling method includes selecting a CPU of relatively less load, when a second thread is generated from a first thread to be processed; determining whether the second thread operates exclusively from the first thread; copying a first storage area assessed by the first thread onto a second storage area managed by the CPU, when the second thread operates exclusively; calculating based on an address of the second storage area and a predetermined value, an offset for a second address for the second thread to access the first storage area; and notifying the CPU of the offset for the second address to convert a first address to a third address for accessing the second storage area.

Abstract: A multi-core system includes multiple processor cores; a bus connected to the processor cores; multiple peripheral devices accessed by the processor cores via the bus; profile information including information concerning access of the peripheral devices by each task assigned to the processor cores; a monitor that based on the profile information, monitors access requests to the peripheral devices from tasks under execution at the processor cores and prohibits an access request that causes contention at the bus; and a scheduler that when the monitor prohibits an access request that causes contention at the bus, switches to a different task.

Abstract: A data allocation method executed by a data allocation system. The data allocation method includes allocating to a first processing apparatus included among a plurality of processing apparatuses and allocating based on a first communication speed of the first processing apparatus, data having communication amount information on a frequency at which the processing apparatuses access the data, and further supplying first priority level information to the first processing apparatus; and exchanging based on variation of a communication speed of at least one processing apparatus among the processing apparatuses, the data or the first priority level information, and data or second priority level information allocated to a second processing apparatus included among the processing apparatuses and having a second communication speed.

Abstract: An interrupt monitoring apparatus includes a storage that stores a given threshold that corresponds to an external interrupt notification; a measuring circuit that measures time that elapses from a time when the external interrupt notification is received until a time when dispatch notification is received from a CPU; a comparing circuit that compares the given threshold and the time measured by the measuring circuit; and an output circuit that outputs to the CPU, a comparison result obtained by the comparing circuit.

Abstract: A memory access controller includes a semiconductor circuit configured to classify into a first group of cores having made an exclusive access request to shared memory and a second group of cores not having made an exclusive access request to the shared memory, multiple cores capable of accessing the shared memory; detect a core having completed the exclusive access among the first group of cores; and send to a core among the first group of cores and standing by for the exclusive access, a notification of release from a standby state, when detecting a core having completed the exclusive access.

Abstract: A processor management method includes setting a master mechanism in a given processor among multiple processors, where the master mechanism manages the processors; setting a local master mechanism and a virtual master mechanism in each of processors other than the given processor among the processors, where the local master mechanism and the virtual master mechanism manage each of the processors; and notifying by the master mechanism, the processors of an offset value of an address to allow a shared memory managed by the master mechanism to be accessed as a continuous memory by the processors.

Abstract: A multi-core processor system includes a given core among multiple cores, wherein the given core is configured to detect execution of a process by the cores; and generate upon detecting the execution of the process, a specific thread that saves state information indicating an executed state of the process and an executed state of each thread to be monitored of the process.

Abstract: A communication method includes performing, by a processor, digital processing for radio communication by multiple communication schemes; combining based on an actual communication state and within a processing capability of the processor, one or more among the communication schemes; and performing concurrent communication.

Abstract: A program executing method is executed by a computer and includes calculating a first power consumption for execution of a first program described by first code; calculating a second power consumption for execution of a second program of a function identical to that of the first program and described by second code; and converting the first program into the second program and executing the second program, if the second power consumption is less than the first power consumption.

Abstract: A data processing apparatus includes a processor configured to receive an interrupt request that is a trigger for execution of an interrupt process executed by the processor; store the received interrupt request to a recording area; calculate based on a time when the interrupt request is received and particular time information read from the recording area, a predicted time when a subsequent interrupt request is to be received; detect a thread to be executed by the processor, among executable threads of the processor; judge based on the calculated predicted time and a current time, whether there is a possibility of the interrupt process being executed while the detected thread is under execution; decide based on a judgment result, whether to execute the detected thread on the processor; and execute the detected thread on the processor, based on a decision result.

Abstract: In an embodiment, a scheduler coordinates timings at which cores execute processes, for any two sequential processes to consecutively be executable. The processes are executed in order scheduled by the scheduler by concentrating on a specific core processes obstructing the consecutive execution such as an external interrupt and an internal interrupt. The scheduler does not always cause processes of another application to be executed during all standby time periods while the scheduler determines whether a length of a standby time period is shorter than a predetermined value, and does not cause any process of the other application to be executed when the length is shorter than that.

Abstract: An image coding apparatus includes a coding and decoding unit configured to selectively encode and decode pictures to be used as a reference among a predetermined number of pictures based on information for discriminating between pictures to be used as a reference and pictures not to be used as a reference, followed by encoding pictures not to be used as a reference among the predetermined number of pictures, an in-loop filter configured to perform filtering with respect to the pictures decoded by the coding and decoding unit, and a control unit configured to suspend power supply to the in-loop filter in response to timing at which the coding and decoding unit encodes the pictures not to be used as a reference.

Abstract: A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process.

Abstract: A communication apparatus includes a first CPU that is capable of executing a communication process at a first processing speed; a measuring unit that measures a first transmission speed when the communication process is executed with a base station; a collecting unit that collects from at least one other apparatus, a second transmission speed between the base station and the apparatus, and a second processing speed of a second CPU included in the other apparatus based on the first transmission speed; a determining unit that determines whether the communication process is to be transferred to the other apparatus, based on the second transmission speed and the second processing speed; and a transferring unit that transfers the communication process to the other apparatus based on a determination result.

Abstract: A multicore processor system is configured to cause among multiple cores, a second core to acquire from a first core that executes a first process, an execution request for a second process and a remaining period from a time of execution of the execution request until an estimated time of completion of the first process; and give notification of a result of the second process from the second core to the first core after an estimated completion time of the first process obtained by adding the remaining period to a start time of the second process.

Abstract: A data sharing system includes communicable terminals and selects a server-client system in which a first terminal is designated as a server and other terminals are designated as clients, when a sum of estimated time for transferring data to the first terminal from the other terminals, estimated time for performing, by the first terminal, arithmetic processing of the data in the first terminal, and estimated time for transferring arithmetically processed data from the first terminal to the other terminals satisfies a real time restriction, and power estimated to be consumed at a time of performing, by the first terminal, the arithmetic processing of the data in the first terminal is less than power estimated to be consumed at a time of performing the arithmetic processing by the other terminals. The data sharing system selects a peer-to-peer system, when the sum does not satisfy the real time restriction in any terminal.

Abstract: A data processing method executed by a first data processing apparatus and includes acquiring process information concerning a first process, in response to a process request for the first process; setting a first process flag included in the process information concerning the first process to indicate “true”; setting a first end flag of the process information concerning the first process to indicate “true” after executing the first process; acquiring process information concerning a second process that is to be executed before a third process that is to be executed subsequent the first process; and determining a process to be executed, based on a second process flag and a second end flag included in the process information concerning the second process.

Abstract: A computer-readable recording medium stores a control program causing a processor of a first terminal to execute a process that includes detecting that a remaining battery level of the first terminal has become less than or equal to a first threshold while a task is under execution by the first terminal; suspending execution of the task upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; transmitting identification information of the task to a second terminal upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; receiving from the second terminal and after transmitting the identification information of the task, information related to a potential of executing the task; and transmitting to the second terminal, information corresponding to the information related to the potential of executing the task.

Abstract: An assignment method executed by a given core of a multi-core processor includes identifying for each core, the number of storage areas to be used by a given thread and the number of storage areas used by threads already assigned; detecting for each core, a highest value from the number of storage areas used by the threads already assigned; determining whether a sum of a greater value of the detected highest value of a core selected as a candidate assignment destination and the number of storage areas to be used by the given thread, and the detected highest value of the cores excluding the selected core, is at most the number of storage areas of the shared resource; and assigning the given thread to the selected core, when the sum is at most the number of storage areas of the shared resource.