Abstract: A data communication method includes registering as a group and by a first data processing device of plural data processing devices, at least one second data processing device capable of communicating with the first data processing device; transmitting by the first data processing device and to the data processing devices, a first reception request for data; transmitting by the first data processing device and to the at least one second data processing device, a second reception request for the data when there is no response to the first reception request from the first data processing devices; and transmitting the data to the second data processing device, by the first data processing device and based on a response from the second data processing device.

Abstract: A data sharing method includes detecting by a first data processing apparatus that is among multiple data processing apparatuses that share data, any one among a shortage of available memory, a change in remaining battery power, a change in a relative positional distance of the first data processing apparatus to a second data processing apparatus that is among the data processing apparatuses, a change in a communication speed of communication with the second data processing apparatus, and an interruption of communication with the second data processing apparatus; and transmitting by the first data processing apparatus to a third data processing apparatus that is among the data processing apparatuses, a shared portion of the data saved in the first data processing apparatus.

Abstract: A data processing method executed by a first data processing apparatus and includes acquiring process information concerning a first process, in response to a process request for the first process; setting a first process flag included in the process information concerning the first process to indicate “true”; setting a first end flag of the process information concerning the first process to indicate “true” after executing the first process; acquiring process information concerning a second process that is to be executed before a third process that is to be executed subsequent the first process; and determining a process to be executed, based on a second process flag and a second end flag included in the process information concerning the second process.

Abstract: A data processing method is executed by a processor, and includes detecting an addition request to add a first device to a first group that includes a plurality of devices; registering the first device into a main group in which devices of the first group are registered, the first device being registered when the first device does not belong to a second group that is different from the first group; registering the first device into a subgroup, when the first device belongs to the second group; and performing by the devices registered in the main group, distributed processing that includes a plurality of tasks.

Abstract: A system includes a CPU; a sensor that detects power of the CPU; a cache memory state monitoring circuit that monitors a state of a cache memory; and a detection circuit that based on a sensor signal from the sensor and a state signal from the cache memory state monitoring circuit, detects a spin state of a program executed by the CPU.

Abstract: A thread processing method that is executed by a multi-core processor, includes supplying a command to execute a first thread to a first processor; judging a dependence relationship between the first thread and a second thread to be executed by a second processor; comparing a first threshold and a frequency of access of any one among shared memory and shared cache memory by the first thread; and changing a phase of a first operation clock of the first processor when the access frequency is greater than the first threshold and upon judging that no dependence relationship exists.

Abstract: A data allocation method executed by a data allocation system. The data allocation method includes allocating to a first processing apparatus included among a plurality of processing apparatuses and allocating based on a first communication speed of the first processing apparatus, data having communication amount information on a frequency at which the processing apparatuses access the data, and further supplying first priority level information to the first processing apparatus; and exchanging based on variation of a communication speed of at least one processing apparatus among the processing apparatuses, the data or the first priority level information, and data or second priority level information allocated to a second processing apparatus included among the processing apparatuses and having a second communication speed.

Abstract: A thread processing method is executed by a specific apparatus included among a plurality of apparatuses, and includes assigning one thread among a plurality of threads to the apparatuses, respectively; acquiring first time information that indicates a time at which the specific apparatus receives an execution result of a corresponding thread from each of the apparatuses; and setting a priority level of an access right to access shared memory that is shared by the apparatuses and the specific apparatus, the setting being based on the first time information and second time information that indicates a time at which reception of execution results of the threads from the apparatuses ends.

Abstract: A scheduling method is executed by a first apparatus among a plurality of apparatuses. The scheduling method includes assigning a process to at least one apparatus among the apparatuses based on a first table that includes each communication strength of the apparatuses; receiving an execution result of the process and a communication strength from the at least one apparatus; and creating the first table based on the received communication strength.

Abstract: A data processing method is executed by a first device, and includes suspending execution of a first process by the first device that belongs to a first device group that includes plural devices; saving based on a request for execution of a second process from a second device that belongs to a second device group that includes plural devices, process information of the first process to shared memory that is set in each of the devices of the first device group and shared by the devices of the first device group; and releasing the saving of the process information of the first process consequent to completion of the execution of the second process.

Abstract: A multi-core processor system includes CPUs; memory; and a memory protect controller that is disposed between the plurality of CPUs and the memory, and that accesses a first memory area consequent to an access request of the CPUs upon application execution and further accesses a second memory area established when the system is booted.

Abstract: An exclusive access control method is executed by a computer having an operating system that when an excluded thread accesses a shared resource, executes a first exclusive access control process of prohibiting the excluded thread from attempting to access the shared resource until exclusive access control is released, the exclusive access control process being executed according to a number of attempts, by the excluded thread, to access the shared resources. The exclusive access control method includes counting by at least one second thread, including the excluded thread and different from a first thread, the number of attempts to access the shared resource, when the first thread executes a second exclusive access control process of allowing the excluded thread to attempt to access the shared resource until the excluded thread is permitted access; and storing to a memory area by the second thread, the counted number of attempts.

Abstract: An endian conversion method is executed by a CPU, and includes executing a program that includes endian conversion setting; and performing, when accessing an address of a main memory indicated in the endian conversion setting, endian conversion of data specified by the address of the main memory.

Abstract: A synchronization method is executed by a multi-core processor system. The synchronization method includes registering based on a synchronous command issued from a first CPU, CPUs to be synchronized and a count of the CPUs into a specific table; counting by each of the CPUs and based on a synchronous signal from the first CPU, an arrival count for a synchronous point, and creating by each of the CPUs, a second shared memory area that is a duplication of a first shared memory area accessed by processes executed by the CPUs; and comparing the first shared memory area and the second shared memory area when the arrival count becomes equal to the count of the CPUs, and based on a result of the comparison, judging the processes executed by the CPUs.

Abstract: A multi-core processor system includes plural CPUs; memory that is shared among the CPUs; and a monitoring unit that instructs a change of assignment of threads to the CPUs based on a first process count stored in the memory and representing a count of processes under execution by the CPUs and a second process count representing a count of processes assigned to the CPUs, respectively.

Abstract: A file sharing method executed by a first terminal, and including selecting from among multiple terminals including the first terminal and based on a remaining battery level of the terminals and a processing time of a shared process, a second terminal to execute the shared process for sharing multiple files among the terminals; and assigning the shared process to the second terminal.

Abstract: A scheduling method is executed by a first CPU and a second CPU. The scheduling method includes acquiring by the first CPU and when a first application is invoked, a first threshold for executing the first application; transmitting by the first CPU, a first threshold to the second CPU; and giving notification to the first CPU by the second CPU when an execution capability of the second CPU is greater than or equal to the first threshold, the notification indicating that the second CPU can execute the first application. The second CPU does not give notification to the first CPU when the execution capability of the second CPU is less than the first threshold.

Abstract: A task scheduling method is executed by a multi-core system and includes reading from a profile memory, first information concerning operation of a first task in a single core system; calculating second information concerning operation of a second task in the multi-core system, based on the first information; and setting based on the second information, an operating environment of a core that executes the second task.

Abstract: A multi-core system enabling cores to simultaneously execute a task includes memory storing task information including for each task, deadline information indicating a deadline for completion of the task and execution period information indicating an execution period of the task, for cache utilization rates of each core, and power information including for each core, source voltage information indicating a source voltage enabling the core to operate and power deriving information deriving power consumption based on the source voltage; and a core configured to: estimate a process period of the task, based on the execution period information and usable-cache size information, and set a task assignment pattern so that within a range where the estimated process period satisfies a real-time restriction by the deadline information, a cache size used by the task and power consumption that is based on the source voltage information and the power deriving information are minimized.

Abstract: A processor management method includes setting a master mechanism in a given processor among multiple processors, where the master mechanism manages the processors; setting a local master mechanism and a virtual master mechanism in each of processors other than the given processor among the processors, where the local master mechanism and the virtual master mechanism manage each of the processors; and notifying by the master mechanism, the processors of an offset value of an address to allow a shared memory managed by the master mechanism to be accessed as a continuous memory by the processors.