Abstract: A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process.

Abstract: A converting apparatus includes a storage configured to store correspondence information that indicates correspondence relations between logical addresses accessed by a processor for booting and physical addresses converted from the logical addresses, the correspondence information being correlated with each type of an event booting the processor; and an address converter configured to select correspondence information related to the type of the event, specify a physical address converted from the logical address accessed by the processor in case of the processor accessing a logical address in response to the event, and control the processor to get a program stored in the storage, the program indicated by the specified physical address.

Abstract: An access method is executed by a multi-core processor system. The access method includes activating a driver that corresponds to a first CPU, based on a start of execution of a first application; starting measurement of an access time period, based on access of a peripheral device; outputting, when the access time period exceeds a predetermined time period, a detection signal to reset the driver; and prohibiting, when the access time period exceeds a predetermined time period, writing into a register retaining data to be written into the peripheral device from the first CPU.

Abstract: A given sensor node, upon determining that data processing requested by another sensor node cannot be completed by the given sensor node, selects a sensor node that based on hop count based information stored in a storage apparatus, is away from a receiver. The given sensor node transmits to the selected sensor node, request notification requesting execution of the data processing exclusive of an executable portion. The given sensor node executes the executable portion, upon receiving securement completion notification indicating that the execution of the data processing indicated in the transmitted request notification can be completed by at least one sensor node among plural sensor nodes.

Abstract: A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores identification information of an assignment destination core for the input destination thread; and a multi-core processor that is configured to update, in the memory unit and when assignment of the input destination thread to a multi-core processor is detected, the identification information of the assignment destination core for the input destination thread; detect a writing request for the given data; identify based on the given data for which the writing request is detected, the updated identification information among information stored in the memory unit; and store the given data to a memory of the assignment destination core that is indicated in the updated identification information and among cores making up the multi-core processor.

Abstract: A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

Abstract: A converting apparatus includes a storage configured to store correspondence information that indicates correspondence relations between logical addresses accessed by a processor for booting and physical addresses converted from the logical addresses, the correspondence information being correlated with each type of an event booting the processor; and an address converter configured to select correspondence information related to the type of the event, specify a physical address converted from the logical address accessed by the processor in case of the processor accessing a logical address in response to the event, and control the processor to get a program stored in the storage, the program indicated by the specified physical address.

Abstract: A multi-core processor system includes a core configured to detect that among cores different from a specific core executing a specific process, a given software different from specific software having a function equivalent to the specific process, is under execution; extract, from a database storing required computing capacities for the plural software and upon detecting that a given software is under execution, requirement values indicating the required computing capacity of the specific software and of the given software; judge for each the cores, whether a sum of the required computing capacities of the specific software and the software is at most a computing capacity value of the core; assign the specific software to a core for which the sum of the required computing capacities is judged to be at most the computing capacity value of the core; and suspend the specific core, upon assigning the specific software to the core.

Abstract: A multi-core processor system includes shared memory shared by cores of a multi-core processor; first cache memories respectively for each of the cores; a second cache memory between the shared memory and the first cache memories, and storing shared data shared by the cores and referred to by at least threads executed by the multi-core processor; a reading unit that reads a value of a given variable from the shared memory; a determining unit that based on a read request for the given variable, determines whether the given variable is shared data or non-shared data that is referred to by only one thread; and a transferring unit that, when the given variable is determined as non-shared data, transfers without using the second cache memory, the value of the given variable to a first cache memory of a core that is a request origin of the read request.

Abstract: An event location analysis system includes a first wireless terminal device. The first wireless terminal device includes a first measurement unit, a second measurement unit, and a first processor. The second measurement unit consumes larger amounts of power than the first measurement unit consumes. The first processor is configured to transmit a first notification signal upon detecting a first event on basis of a measurement value of the first measurement unit. The first processor is configured to start the second measurement unit upon receiving a second notification signal. The first processor is configured to activate a measurement operation of the first measurement unit and a measurement operation of the second measurement unit after the second measurement unit is started. The first processor is configured to stop the measurement operation of the second measurement unit after a predetermined time has elapsed since the start of the second measurement unit.

Abstract: A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request.

Abstract: A multicore processor system includes a processor configured to detect any among a switching process and an assignment process of applications in a multicore processor; acquire upon detecting any among the switching process and the assignment process, a priority level concerning execution of each application assigned to each core of the multicore processor and number of accesses of a shared resource shared by the multicore processor; determine an access ratio of an application whose priority level is highest to each of application remaining after excluding the application whose priority level is highest, among the assigned applications, by comparing the number of accesses by each remaining application and the number of accesses by the application whose priority level is highest; notify an arbiter circuit of the determined access ratios; and arbitrate using the arbiter circuit, the access of the shared resource by the multicore processor, based on the access ratios.

Abstract: A communications apparatus is included among a communications apparatus group arranged in a given area and capable of communicating with a nearby communications apparatus. The communications apparatus includes a sensor that detects a given property at a location of the communications apparatus; communications circuitry that receives from the nearby communications apparatus, a detection result that is obtained by another communications apparatus, for the given property at the location of the other communications apparatus; a processor that determines whether a difference between the detection result received by the communications circuitry and a detection result of the sensor is a given amount or less.

Abstract: A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

Abstract: A determining method includes obtaining by each monitoring apparatus among plural monitoring apparatuses disposed encompassing a given area having plural wireless communications apparatuses, hop count information that indicates a hop count of a wireless signal transmitted by one wireless communications apparatus among the wireless communications apparatuses and received by the monitoring apparatus via multi-hop communication by the wireless communications apparatuses; calculating by each monitoring apparatus, an estimated line that represents candidates of a position of the one wireless communications apparatus, the estimated line being calculated from an estimated distance between the monitoring apparatus and the one wireless communications apparatus, based on the hop count; correcting by each monitoring apparatus, the calculated estimated line based on information indicating a node-less area in which no wireless communications apparatus of the given area is present; and determining the position of the one w

Abstract: A sensor node executes any one among a first operation by which another sensor node is requested to execute data process and if the request is not accepted the sensor node starts executing the data processing after waiting for charging and a second operation by which the sensor node starts executing the data processing after waiting for charging, without requesting the data processing to be executed. The sensor node compares an expected value of a first time that elapses until execution is started by the sensor node or the other sensor node when the first operation is executed, and a second time that elapses until execution is started by the sensor node when the second operation is executed. Based on the comparison result, the sensor node executes among the first operation and the second operation, the operation for which the time that elapses until execution is started is shorter.

Abstract: A given communications apparatus is included among plural first communications apparatuses, among which at least execution results of data processing of the given communications apparatus is communicated by multi-hop communication whereby, the execution results are transmitted to a second communications apparatus that performs a process based on the execution results.

Abstract: A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.

Abstract: A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

Abstract: A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores identification information of an assignment destination core for the input destination thread; and a multi-core processor that is configured to update, in the memory unit and when assignment of the input destination thread to a multi-core processor is detected, the identification information of the assignment destination core for the input destination thread; detect a writing request for the given data; identify based on the given data for which the writing request is detected, the updated identification information among information stored in the memory unit; and store the given data to a memory of the assignment destination core that is indicated in the updated identification information and among cores making up the multi-core processor.