Abstract: In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

Abstract: In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns; a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.

Abstract: In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

Abstract: A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

Abstract: In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

Abstract: In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns: a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.

Abstract: In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.

Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.