Abstract: Expression of matrix metalloproteinase 1 is suppressed. A matrix metalloproteinase 1 expression suppression agent of this disclosure contains, as an active ingredient, at least one selected from the group consisting of Saxifraga sarmentosa, an extract of Saxifraga sarmentosa, rosemary, an extract of rosemary, licorice, an extract of licorice, Melissa officinalis, an extract of Melissa officinalis, wild thyme, an extract of wild thyme, hop, and an extract of hop.

Abstract: An objective of the present invention is to provide a hot melt composition which has a high form maintaining property at a high temperature, is well-balanced between adhesion and removability to a substrate, hardly sags, has less volatile matter content and is excellent in hygiene. The present invention relates to a hot melt composition comprising: (A) a thermoplastic block copolymer which is a copolymer of a vinyl-based aromatic hydrocarbon and a conjugated diene compound, (B1) a hydrocarbon-based oil having an aniline point of 135° C. or more, and (C) a wax modified with a carboxylic acid and/or a carboxylic acid anhydride.

Abstract: An objective of the present invention is to provide a hot melt composition having a high form maintaining property at a high temperature and being in excellent adhesion to a substrate and in disassembly. The present invention relates to a hot melt composition comprising: (A1) a styrene-ethylene-ethylene/propylene-styrene block copolymer (SEEPS) and (B1) a hydrocarbon-based oil having an aniline point of 135° C. or more.

Abstract: An objective of the present invention is to provide a hot melt composition which (i) is excellent in adhesion and heat resistance, and (ii) is not transferred to a surface of a substrate when the substrates pre-coated with the hot melt composition are stacked and stored. The present invention relates to a hot melt composition comprising: a hot melt composition comprising: (A) an amorphous poly-?-olefin, (B) a crystalline propylene-based polymer, (C) a tackifier resin, and (D) a Fischer-Tropsch wax, wherein an amount of the Fischer-Tropsch wax (D) based on 100 parts by weight of the total amount of the components (A) to (D) is 1 to 15 parts by weight.

Abstract: An objective of the present invention is to provide a hot melt composition which (i) is excellent in adhesion and heat resistance, and (ii) is not transferred to a surface of a substrate when the substrates pre-coated with the hot melt composition are stacked and stored. The present invention relates to a hot melt composition comprising: (A) an amorphous poly-?-olefin, (B) a crystalline propylene-based polymer, and (C) a tackifier resin, wherein the amorphous poly-?-olefin (A) comprises (A1) an amorphous poly-?-olefin having a softening point of 150° C. or more.

Abstract: An objective of the present invention is to provide a hot melt composition which has a high form maintaining property at a high temperature, is well-balanced between adhesion and removability to a substrate, hardly sags, has less volatile matter content and is excellent in hygiene. The present invention relates to a hot melt composition comprising: (A) a thermoplastic block copolymer which is a copolymer of a vinyl-based aromatic hydrocarbon and a conjugated diene compound, (B1) a hydrocarbon-based oil having an aniline point of 135° C. or more, and (C) a wax modified with a carboxylic acid and/or a carboxylic acid anhydride.

Abstract: An objective of the present invention is to provide a hot melt composition having a high form maintaining property at a high temperature and being in excellent adhesion to a substrate and in disassembly. The present invention relates to a hot melt composition comprising: (A1) a styrene-ethylene-ethylene/propylene-styrene block copolymer (SEEPS) and (B1) a hydrocarbon-based oil having an aniline point of 135° C. or more.

Abstract: A method to prevent stress corrosion cracking of a storage canister 1, wherein stress corrosion cracking is prevented by applying a compressive stress to a range where a tensile residual stress is generated on a metallic body 2 by welding a cover 4 to a top 2a of the body 2. A first compressive stress is applied beforehand to a range L of the body 2 where a tensile residual stress is expected to be generated by the welding of the cover 4, the tensile residual stress is canceled by welding the cover 4 with a compressive residual stress generated in the range L, and then a second compressive stress is applied so as to generate a compressive residual stress over the range L.

Abstract: A method to prevent stress corrosion cracking of a storage canister 1, wherein stress corrosion cracking is prevented by applying a compressive stress to a range where a tensile residual stress is generated on a metallic body 2 by welding a cover 4 to a top 2a of the body 2. A first compressive stress is applied beforehand to a range L of the body 2 where a tensile residual stress is expected to be generated by the welding of the cover 4, the tensile residual stress is canceled by welding the cover 4 with a compressive residual stress generated in the range L, and then a second compressive stress is applied so as to generate a compressive residual stress over the range L.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, an isolation layer, and a guard ring layer of the second conductivity type. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer to be joined to the second semiconductor layer. The isolation layer surrounds a periphery of the third semiconductor layer and is deeper than the third semiconductor layer. The guard ring layer is provided between the third semiconductor layer and the isolation layer, adjacent to the third semiconductor layer, and deeper than the third semiconductor layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate with a p-type conductivity, a buried layer with an n-type conductivity provided on the semiconductor substrate, a back gate layer with a p-type conductivity provided on the buried layer, a drain layer with an n-type conductivity provided on the back gate layer, a source layer with an n-type conductivity provided spaced from the drain layer, a gate electrode provided in a region immediately above a portion of the back gate layer between the drain layer and the source layer, and a drain electrode in contact with a part of an upper surface of the drain layer. A thickness of the drain layer in a region immediately below a contact surface between the drain layer and the drain electrode is half a total thickness of the back gate and drain layers in the region.

Abstract: A semiconductor device includes an n-type first guard ring layer provided between an emitter layer and a collector layer on a surface side of a base layer, and having a higher n-type impurity concentration than the base layer, and an n-type second guard ring layer provided between the first guard ring layer and a buried layer, connected to the first guard ring layer and the buried layer, and having a higher n-type impurity concentration than the base layer. The first guard ring layer has an n-type impurity concentration profile decreasing toward the second guard ring layer side, and the second guard ring layer has an impurity concentration profile decreasing toward the first guard ring layer side.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of a second conductivity type provided on the semiconductor substrate, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a first well of the second conductivity type provided on the second semiconductor layer, a second well of the first conductivity type provided on part of the first well, a source layer of the second conductivity type provided on part of the second well and separated from the first well, a back gate layer of the first conductivity type provided on another part of the second well, and a drain layer of the second conductivity type provided on another part of the first well. The second semiconductor layer and the second well are separated from each other by the first well.

Abstract: A first semiconductor layer extends from the element region to the element-termination region, and functions as a drain of the MOS transistor. A second semiconductor layer extends, below the first semiconductor layer, from the element region to the element-termination region. A third semiconductor layer extends from the element region to the element-termination region, and is in contact with the second semiconductor layer to function as a drift layer of the MOS transistor. A distance between a boundary between the first semiconductor layer and the field oxide film, and the end portion of the third semiconductor layer on the fifth semiconductor layer side in the element region is smaller than that between a boundary between the first semiconductor layer and the field oxide layer and an end portion of the third semiconductor layer on the fifth semiconductor layer side in the element-termination region.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, an isolation layer, and a guard ring layer of the second conductivity type. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer to be joined to the second semiconductor layer. The isolation layer surrounds a periphery of the third semiconductor layer and is deeper than the third semiconductor layer. The guard ring layer is provided between the third semiconductor layer and the isolation layer, adjacent to the third semiconductor layer, and deeper than the third semiconductor layer.

Abstract: A semiconductor device includes an n-type first guard ring layer provided between an emitter layer and a collector layer on a surface side of a base layer, and having a higher n-type impurity concentration than the base layer, and an n-type second guard ring layer provided between the first guard ring layer and a buried layer, connected to the first guard ring layer and the buried layer, and having a higher n-type impurity concentration than the base layer. The first guard ring layer has an n-type impurity concentration profile decreasing toward the second guard ring layer side, and the second guard ring layer has an impurity concentration profile decreasing toward the first guard ring layer side.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate with a p-type conductivity, a buried layer with an n-type conductivity provided on the semiconductor substrate, a back gate layer with a p-type conductivity provided on the buried layer, a drain layer with an n-type conductivity provided on the back gate layer, a source layer with an n-type conductivity provided spaced from the drain layer, a gate electrode provided in a region immediately above a portion of the back gate layer between the drain layer and the source layer, and a drain electrode in contact with a part of an upper surface of the drain layer. A thickness of the drain layer in a region immediately below a contact surface between the drain layer and the drain electrode is half a total thickness of the back gate and drain layers in the region.

Abstract: A first semiconductor layer extends from the element region to the element-termination region, and functions as a drain of the MOS transistor. A second semiconductor layer extends, below the first semiconductor layer, from the element region to the element-termination region. A third semiconductor layer extends from the element region to the element-termination region, and is in contact with the second semiconductor layer to function as a drift layer of the MOS transistor. A distance between a boundary between the first semiconductor layer and the field oxide film, and the end portion of the third semiconductor layer on the fifth semiconductor layer side in the element region is smaller than that between a boundary between the first semiconductor layer and the field oxide layer and an end portion of the third semiconductor layer on the fifth semiconductor layer side in the element-termination region.

Abstract: A semiconductor device includes a diode formed by making use of a DMOS transistor structure. In addition to such a DMOS transistor structure, the semiconductor device includes a second buried layer of the first conductivity type being provided on a first buried layer of a second conductivity type that is in a floating state. Moreover, the second buried layer of the first conductivity type and a second diffusion region of the first conductive type are connected by a first diffusion region of the first conductivity type. A first electrode is set as anode, and a second electrode and a third electrode are short-circuited and set as cathode.

Abstract: A first semiconductor layer extends from the element region to the element-termination region, and functions as a drain of the MOS transistor. A second semiconductor layer extends, below the first semiconductor layer, from the element region to the element-termination region. A third semiconductor layer extends from the element region to the element-termination region, and is in contact with the second semiconductor layer to function as a drift layer of the MOS transistor. A distance between a boundary between the first semiconductor layer and the field oxide film, and the end portion of the third semiconductor layer on the fifth semiconductor layer side in the element region is smaller than that between a boundary between the first semiconductor layer and the field oxide layer and an end portion of the third semiconductor layer on the fifth semiconductor layer side in the element-termination region.