Abstract: In a semiconductor device according to the present invention, a pair of element regions of a second conductivity type are formed so as to be electrically isolated from each other on a semiconductor substrate of a first conductivity type, a complementary MOS transistor is formed in one of the element regions of the second conductivity type, and a double-diffused MOS transistor is formed in the other element region of the second conductivity type. The complementary MOS transistor is of a surface channel type in which N- and P-channel MOS transistors are respectively formed in a pair of well diffusion layers of the first and second conductivity types formed in the element region of the second conductivity type, and conductivity types of the respective gate electrodes of the N- and P-channel MOS transistors are different from those of the respective well diffusion layers.

Abstract: In a MOS-type integrated circuit, a source and a gate of a double diffusion MOSFET of an n-channel type and a drain and a gate of a double diffusion MOSFET of a p-channel type are in an island region surrounded by an n-type annular contact region having high impurity concentration. An n epitaxial layer, in each island region, is used for the sources and drains of both MOSFETs. The drain electrode of the p-channel MOSFET is connected to the gate electrode of the n-channel MOSFET. With this structure, the power consumption of the circuit is decreased, and the operating speed thereof is increased.

Abstract: A semiconductor device comprises a substrate including a p-type first semiconductor region, an n-type second semiconductor region formed in the first semiconductor region, a first insulating layer formed on surfaces of the first semiconductor region and the second semiconductor region, a first conductive layer formed, via the first insulating layer, over the surface of the second semiconductor region, and set at substantially the same potential as that of the second semiconductor region, an n-type third semiconductor region formed to be spaced apart from the second semiconductor region and formed in the first semiconductor region so that a part of the third semiconductor region overlaps a part of the first conductive layer, via the first insulating layer, a second conductive layer connected to the third semiconductor region through an opening formed in the first insulating layer, and a wiring layer formed on a second insulating layer provided on surfaces of the first and second conductive layers.

Abstract: First and second single crystal silicon substrates are integrated, by means of a thermal treatment, with first and second silicon oxide films formed on surfaces of said respective first and second single crystal silicon substrates in contact with each other. More specifically, an insulating region is formed by integrating first and second silicon oxide films formed on the first and second single crystal silicon substrates. First and second semiconductor regions constituted by the first and second single crystal silicon substrates are electrically isolated by the insulating region. As a result, it is possible to reduce the width of the depletion layer generated in the second semiconductor region by the influence of the first semiconductor region in which an element is formed. A back gate region formed in the second semiconductor region and the first semiconductor region, in which an element is not formed, are held substantially at an equal potential.

Abstract: A semiconductor device comprising a semiconductor substrate, a field effect transistor formed in the substrate, and a diode connected to the field effect transistor and formed on the insulation film formed on the substrate. Since the diode is electrically insulated from the substrate by the insulation film, no parasitic PNPN thyristor is formed in the semiconductor substrate. Therefore, a latch-up is prevented from occurring in the semiconductor device.

Abstract: First and second single crystal silicon substrates are integrated, by means of a thermal treatment, with first and second silicon oxide films formed on surfaces of said respective first and second single crystal silicon substrates in contact with eacth other. More specifically, an insulating region is formed by integrating first and second silicon oxide films formed on the first and second single crystal silicon substrates. First and second semiconductor regions constituted by the first and second single crystal silicon substrates are electrically isolated by the insulating region. As a result, it is possible to reduce the width of the depletion layer generated in the second semiconductor region by the influence of the first semiconductor region in which an element is formed. A back gate region formed in the second semiconductor region and the first semiconductor region, in which an element is not formed, are held substantially at an equal potential.

Abstract: In a semiconductor device according to the present invention, a pair of element regions of a second conductivity type are formed so as to be electrically isolated from each other on a semiconductor substrate of a first conductivity type, a complementary MOS transistor is formed in one of the element regions of the second conductivity type, and a double-diffused MOS transistor is formed in the other element region of the second conductivity type. The complementary MOS transistor is of a surface channel type in which N- and P-channel MOS transistors are respectively formed in a pair of well diffusion layers of the first and second conductivity types formed in the element region of the second conductivity type, and conductivity types of the respective gate electrodes of the N- and P-channel MOS transistors are different from those of the respective well diffusion layers.

Abstract: There is disclosed an NPN transistor comprising collector region of N conductivity type, base region of P conductivity type formed in the collector region, and emitter region of N conductivity type formed in the collector region. The collector and emitter regions define therebetween a planar PN junction. The NPN transistor further comprises a field plate electrode layer, when the transistor is viewed from above, extending from the periphery of the base region to the collector region. The field plate electrode layer comprises P conductivity semiconductor portion and N conductivity semiconductor portion. The P conductivity semiconductor portion is on the side of the base region. The N conductivity semiconductor portion is on the side of the collector region.