Abstract: According to one embodiment, a semiconductor device includes a p-type semiconductor layer, an n-type source region, an insulator, an n-type semiconductor region, an n-type drain region, a p-type channel region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and an electrode. The source region is provided on a surface of the p-type semiconductor layer. The insulator is provided in a trench formed extending in a thickness direction of the p-type semiconductor layer from the surface of the p-type semiconductor layer. The n-type semiconductor region is provided on the surface of the p-type semiconductor layer between the source region and the insulator. The drain region is provided on the surface of the p-type semiconductor layer between the source region and the n-type semiconductor region and separated from the source region and the n-type semiconductor region.

Abstract: A semiconductor device includes a P-type substrate 1, an N-type buried layer 2, a P-type buried layer 3, N-type epitaxial layers 4, P-type diffusion layers 6, P-type diffusion layers 8, P-type diffusion layers 11, first electrodes formed on the P-type diffusion layers 11, N-type diffusion layers 9, P-type diffusion layers 12, N-type diffusion layers 13, second electrodes formed on the P-type diffusion layers 12 and the N-type diffusion layers 13, and gate electrodes 10 short-circuited with the second electrodes. The N-type buried layer 2 is in a floating state.

Abstract: A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

Abstract: The sensitivity, diffraction efficiency, etc. of hologram recording materials is improved. Disclosed is a resin composition for a hologram recording material, the resin composition comprising: a photosensitive component comprising (a) a monomer having a vinyloxy group, (b) a compound having a (meth)acryloxy group, and (c) a photopolymerization initiator; and a prepolymer component, wherein the component (a) is designed so as to be relatively higher or lower in refractive index than the prepolymer component.

Abstract: A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

Abstract: A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

Abstract: A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

Abstract: A method of determining the present electric field state of a mobile station also in view of an uplink electric field state is disclosed. A TPC bit counter is supplied with a received signal processed by a baseband processor, and counts TPC bits contained in one radio frame. An electric field state determining unit measures the electric field strength of the received signal from the base station which has been received by an RF receiver.

Abstract: A semiconductor device having a diffusion layer comprising: a semiconductor substrate of a first conductivity type comprising first and second portions having first and second impurity density, respectively, the first portion located so as to surround the second portion; a transistor having a first diffusion layer and a gate electrode, the first diffusion layer of the transistor formed in the first portion of the semiconductor substrate and having a third impurity density; and a semiconductor well of a second conductivity type formed between the first portion and the second portion of the semiconductor substrate, the semiconductor well having a fourth impurity density and formed so as to surround the first portion of the semiconductor substrate and located in the second portion of the semiconductor substrate.

Abstract: A portable radio communication apparatus which allows reduction in power consumption is disclosed. An input device has a special key and a plurality of general keys. A microprocessor changes an operation mode from a power-saving mode to a normal operation mode when receiving an interrupt signal. A controller connected to the special key outputs the interrupt signal to the microprocessor when one of the general keys is operated. When the special key is operated, the controller controls a backlit LCD without outputting the interrupt signal such that the LCD is backlighted and predetermined information is displayed on the LCD.

Abstract: A method of determining the present electric field state of a mobile station also in view of an uplink electric field state is disclosed. A TPC bit counter is supplied with a received signal processed by a baseband processor, and counts TPC bits contained in one radio frame. An electric field state determining unit measures the electric field strength of the received signal from the base station which has been received by an RF receiver.

Abstract: A semiconductor device includes a substrate and a semiconductor layer of a first conductivity type, formed over the substrate via an insulating layer, the semiconductor layer having a protective diode. The protective diode has a first diffusion layer of a second conductivity type, formed in the semiconductor layer, a second diffusion layer of the second conductivity type, formed in the semiconductor layer, the second diffusion layer being isolated from the first diffusion layer, a third diffusion layer of the first conductivity type, formed in a region of the semiconductor layer, the region being sandwiched between the first and the second diffusion layers, the third diffusion layer being contact with the second diffusion layer, a first electrode formed as being contact with the first diffusion layer and a second electrode formed as being contact with the second and the third diffusion layers.

Abstract: There is provided a semiconductor device that has a reduced parasitic capacitance bonding pad structure using a silicon-on-insulator substrate. In the semiconductor device according to the present invention, a pn junction is formed by forming a semiconductor region, that has a different conductivity type from the active layer, in an active layer below a bonding pad to generate a depletion layer. Thus, a parasitic capacitance connected to the bonding pad can be reduced by a capacitance that is formed by the generation of this depletion layer. Also, a leakage current from the bonding pad can be suppressed by the generation of the pn junction.

Abstract: A MOSFET formed on an SOI substrate secures a high withstand voltage and a reduced element area. The SOI substrate includes an insulator layer and an n−-type semiconductor layer formed on the insulator layer. The MOSFET consists of a p-type impurity diffusion region formed on the semiconductor layer, an n+-type source region formed in a surface area in the p-type impurity diffusion region, a gate insulating layer formed on the p-type impurity diffusion region and covering a region between the source region and the semiconductor layer, a gate electrode formed on the gate insulating layer, an n+-type drain region formed on the semiconductor layer at a predetermined position separated from the p-type impurity diffusion region, and an n-type well formed around the drain region. The impurity concentration of the n-type well is lower than that of the drain region and higher than that of the semiconductor layer.

Abstract: The present invention relates to a semiconductor package having lead pins of lead frame for outwardly extending terminals of electrodes of a semiconductor chip embedded in a mold resin. The semiconductor package according to the present invention comprises flat lead fins connected to respective sides of a bed portion of a lead frame, an insulation film for covering at least one side of each of the lead fins, and lead pins formed on a surface of the insulation film, the lead pins being disposed at a predetermined pitch.

Abstract: A field effect transistor comprises a first conductive type semiconductor substrate, a second conductive type source region formed on the semiconductor substrate, a second conductive type drain region formed on the semiconductor substrate and non-contacting the source region, and a gate electrode formed on a channel region between the source region and the drain region through a gate insulating film, wherein the thickness of the gate insulating film is thickened at least in a two-step manner in a direction from the source region to the drain region, impurity concentration of the respective channel regions under the gate insulating film having a different film thickness is different, and impurity concentration of the channel region under the thick film portion of the gate insulating film is lower than that of the channel region under the thin film portion of the gate insulating film.

Abstract: A lateral MOSFET includes a back gate region, a part of its surface being a channel region. The back gate region surrounds the drain region, while being in contact with a part of the periphery of the drain region. With this configuration, when a high voltage electrostatic surge appears at the drain electrode, a surge current will disperse from the drain region toward the surrounding back gate region. As a result, a rise in the electric potential at the drain region is suppressed. Thus, the electric potential will not exceed the dielectric strength of the gate insulating film to suppress a breakdown of the gate insulating film and an electrostatic breakdown of the device.

Abstract: A semiconductor layer made of an epitaxial growing layer (16) is formed on the surface of a p.sup.- -type silicon semiconductor substrate (11), first impurity regions are formed by p.sup.+ -type buried regions (171, 172) and a p-type impurity regions (221, 222) throughout the semiconductor layer from its surface to the semiconductor substrate so as to divide said semiconductor layer into side element regions (161, 162) and a central island region (163). An anode layer obtained by alternately arranging n.sup.+ -type impurity regions (251 to 253) and p.sup.+ -type impurity regions (231, 232) is formed in surface regions of the pair of impurity regions, and cathode regions made of p-type impurity regions (231, 232) are formed in the element regions of the semiconductor layer. Gate electrodes are formed to be opposite to each other through a gate insulating film in p-n junction portions constituted by the n.sup.+ -type impurity regions (251, 252) the p-type impurity regions (221, 222), and an n.sup.

Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type, a first well of a second conductivity type formed on the semiconductor substrate of the first conductivity type, a first impurity diffusion layer of the first conductivity type formed on the well without contacting the semiconductor substrate, a second impurity diffusion layer of the second conductivity type which surrounds the first impurity diffusion layer and has an impurity concentration which is higher than that of the first impurity diffusion layer, a third impurity diffusion layer of the first conductivity type formed within the second impurity diffusion layer so as to contact neither the semiconductor substrate nor the first impurity diffusion layer, a source electrode connected to both the second impurity diffusion layer and the third impurity diffusion layer, a gate electrode which is formed between the first impurity diffusion layer and the third impurity diffusion layer and formed on the second impurity diffus

Abstract: A semiconductor device comprises first and second island regions of a first conductivity type formed closely to each other in the surface area of a semiconductor substrate, first-and second-channel type MOS FETs formed in the first island region, and a high impurity concentration region of the first conductivity type having an impurity concentration higher than the island regions and formed between the substrate and at least one of the first and second island regions, the high impurity concentration region being formed to surround the island regions.