Abstract: A first pulse selector outputs an output signal of a variable frequency divider to phase frequency detectors in a time division manner. A second pulse selector outputs a reference signal from a reference signal source to the phase frequency detectors in a time division manner. Outputs of the phase frequency detectors are provided, respectively, for multiple disposed charge pump circuits.

Abstract: A lock detector (8) detects an unlocked state from an output of a phase frequency comparator (1). A counter (9) counts a reference signal, in a case where an unlocked state is detected by the lock detector (8). A parameter controlling circuit (10) acquires the count value of the counter (9), and controls switching on and off of a switch (12) for a D/A converter (11) that generates a signal to be added to an output of a loop filter (3), and the output voltage of the D/A converter (11) so that the count value of the counter (9) falls within a set value.

Abstract: A phase-frequency comparator compares a reference signal with an output signal from a variable frequency divider, and outputs an up signal of frequency and a down signal of frequency depending on results of the comparison. An AND circuit performs an AND operation between the up signal and the down signal, and outputs a result of the operation as a retiming si al CLKretime. A flip-flop circuit holds an output signal from a frequency control circuit at timing of the output signal from the AND circuit, and outputs the held output signal. At ?? modulator determines a division ratio for the variable frequency divider on the basis of the output from the flip-flop circuit.

Abstract: A signal generating circuit includes a control voltage setting unit (CVSU) configured to set a control voltage for a chirp signal using voltage-frequency characteristics indicating characteristics of an output frequency versus voltage; a VCO configured to alter the frequency of its output signal by the control voltage; a quadrature demodulator configured to perform quadrature demodulation of the output signal of the VCO to generate an inphase signal and a quadrature signal orthogonal to each other; and a frequency detector configured to detect the frequency of the output signal of the VCO on the basis of the inphase signal and quadrature signal. The CVSU corrects the control voltage by using the voltage-frequency characteristics derived from relationships between the control voltage and the frequency of the output signal of the VCO. The VCO generates the chirp signal based on the control voltage corrected by the CVSU.

Abstract: A variable gain amplifier (1) includes: a signal transmission circuit (10, 20) including amplifying transistor units (111 to 11N, and 211 to 21N) connected in parallel between a signal input port (2P, 2N) and a signal output port (3P, 3N); a load circuit (40) connected between a supply line of power supply voltage (VDD) and an output end of the signal transmission circuit (10, 20); a signal short circuit (30) including a short-circuit transistor unit (31) connected between the supply line of the power supply voltage (VDD) and an input end of the signal transmission circuit (10, 20), a constant-current source circuit (42), and a transistor control circuit (46). The transistor control circuit (46) selects transistor units to be turned on, from among the amplifying transistor units (111 to 11N, and 211 to 21N) and the short-circuit transistor unit (31), and supplies control voltages for turning on the selected transistor units.

Abstract: A first transistor, a second transistor, a third transistor, and a fourth transistor, their source terminals being grounded, are provided. Further, a first feedback circuit connected between a gate terminal and a drain terminal in the first transistor, and having first impedance, a second feedback circuit connected between a gate terminal and a drain terminal in the second transistor, and having the first impedance, a current source for outputting a current, a first load circuit connected between the drain terminal of the first transistor and a first output terminal of the current source, and having second impedance, and a second load circuit connected between the drain terminal of the second transistor and a second output terminal of the current source, and having the second impedance are provided.

Abstract: There are provided: a table memory to store a relation between a control code and gains of variable gain amplifiers; a gain controller to apply the gains to the variable gain amplifiers; an amplitude phase detector to detect amplitude and a phase from an output signal of the vector sum phase shifter; an amplitude phase recorder to record, when the gains are applied by the gain controller, a combination of a control code corresponding to said gains and the amplitude and the phase detected by the detector; and a table calibrator to find a phase shift characteristic of a vector summed part from records of the amplitude phase recorder and calibrate the relation between a control code and gains recorded in the table memory by using the phase shift characteristic.

Abstract: A first frequency accumulator (7a) operates using an output signal of a variable frequency divider (3) as a clock. A second frequency accumulator (7b) operates using a reference signal from a reference signal source (1) as a clock. A comparison operating circuit (11) compares the output values of the first frequency accumulator (7a) and the second frequency accumulator (7b), and calculates a parameter so that a result of the comparison falls within a set value. A digital-analog converter (9) outputs a signal to be added to an output of a loop filter (6) depending on the parameter output from the comparison operating circuit (11).

Abstract: A first frequency accumulator (7a) operates using an output signal of a variable frequency divider (3) as a clock. A second frequency accumulator (7b) operates using a reference signal from a reference signal source (1) as a clock. A comparison operating circuit (11) compares the output values of the first frequency accumulator (7a) and the second frequency accumulator (7b), and calculates a parameter so that a result of the comparison falls within a set value. A digital-analog converter (9) outputs a signal to be added to an output of a loop filter (6) depending on the parameter output from the comparison operating circuit (11).

Abstract: A lock detector (8) detects an unlocked state from an output of a phase frequency comparator (1). A counter (9) counts a reference signal, in a case where an unlocked state is detected by the lock detector (8). A parameter controlling circuit (10) acquires the count value of the counter (9), and controls switching on and off of a switch (12) for a D/A converter (11) that generates a signal to be added to an output of a loop filter (3), and the output voltage of the D/A converter (11) so that the count value of the counter (9) falls within a set value.

Abstract: Provided is a polyphase filter, which is capable of achieving amplitude matching and phase matching while achieving a low insertion loss with a single-stage configuration. A first variable resistor and a second variable resistor have resistance values that are equal to each other, and the resistance values are set so as to correct an amplitude error between orthogonal signals of outputs of a first output terminal to a fourth output terminal. A first variable capacitor, a second variable capacitor, a third variable capacitor, and a fourth variable capacitor have capacitance values that are equal to one another, and the capacitance values are set so as to correct a phase error between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal.

Abstract: A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.

Abstract: A variable gain amplifier (1) includes: a signal transmission circuit (10, 20) including amplifying transistor units (111 to 11N, and 211 to 21N) connected in parallel between a signal input port (2P, 2N) and a signal output port (3P, 3N); a load circuit (40) connected between a supply line of power supply voltage (VDD) and an output end of the signal transmission circuit (10, 20); a signal short circuit (30) including a short-circuit transistor unit (31) connected between the supply line of the power supply voltage (VDD) and an input end of the signal transmission circuit (10, 20), a constant-current source circuit (42), and a transistor control circuit (46). The transistor control circuit (46) selects transistor units to be turned on, from among the amplifying transistor units (111 to 11N, and 211 to 21N) and the short-circuit transistor unit (31), and supplies control voltages for turning on the selected transistor units.

Abstract: A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.

Abstract: Provided is a polyphase filter, which is capable of achieving amplitude matching and phase matching while achieving a low insertion loss with a single-stage configuration. A first variable resistor and a second variable resistor have resistance values that are equal to each other, and the resistance values are set so as to correct an amplitude error between orthogonal signals of outputs of a first output terminal to a fourth output terminal. A first variable capacitor, a second variable capacitor, a third variable capacitor, and a fourth variable capacitor have capacitance values that are equal to one another, and the capacitance values are set so as to correct a phase error between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal.

Abstract: There are provided: a table memory to store a relation between a control code and gains of variable gain amplifiers; a gain controller to apply the gains to the variable gain amplifiers; an amplitude phase detector to detect amplitude and a phase from an output signal of the vector sum phase shifter; an amplitude phase recorder to record, when the gains are applied by the gain controller, a combination of a control code corresponding to said gains and the amplitude and the phase detected by the detector; and a table calibrator to find a phase shift characteristic of a vector summed part from records of the amplitude phase recorder and calibrate the relation between a control code and gains recorded in the table memory by using the phase shift characteristic.

Abstract: A signal generating circuit includes a control voltage setting unit (CVSU) configured to set a control voltage for a chirp signal using voltage-frequency characteristics indicating characteristics of an output frequency versus voltage; a VCO configured to alter the frequency of its output signal by the control voltage; a quadrature demodulator configured to perform quadrature demodulation of the output signal of the VCO to generate an inphase signal and a quadrature signal orthogonal to each other; and a frequency detector configured to detect the frequency of the output signal of the VCO on the basis of the inphase signal and quadrature signal. The CVSU corrects the control voltage by using the voltage-frequency characteristics derived from relationships between the control voltage and the frequency of the output signal of the VCO. The VCO generates the chirp signal based on the control voltage corrected by the CVSU.

Abstract: An active balun circuit includes a CG transistor having a source terminal thereof connected to an input terminal and a gate terminal thereof grounded, a CS transistor having a gate terminal thereof connected to the input terminal and a source terminal thereof grounded, an asymmetrical transformer, a first output terminal, and a second output terminal. The asymmetrical transformer includes a primary coil and a secondary coil. The primary coil includes a first inductor connected to the CG transistor and a second inductor connected to the CS transistor. The secondary coil includes a third inductor associated with the first inductor and a fourth inductor associated with the second inductor. The first output terminal outputs a first signal generated at the third inductor, and the second output terminal outputs a second signal generated at the fourth inductor.

Abstract: An active balun circuit includes a CG transistor having a source terminal thereof connected to an input terminal and a gate terminal thereof grounded, a CS transistor having a gate terminal thereof connected to the input terminal and a source terminal thereof grounded, an asymmetrical transformer, a first output terminal, and a second output terminal. The asymmetrical transformer includes a primary coil and a secondary coil. The primary coil includes a first inductor connected to the CG transistor and a second inductor connected to the CS transistor. The secondary coil includes a third inductor associated with the first inductor and a fourth inductor associated with the second inductor. The first output terminal outputs a first signal generated at the third inductor, and the second output terminal outputs a second signal generated at the fourth inductor.

Abstract: A control unit executes sensing of a fuel property of fuel based on a physical value, which is related to a combustion state of the fuel in an internal combustion engine, when it is determined that a predetermined prerequisite operational condition for the sensing of the fuel property is satisfied upon occurrence of at least one of consumption of a predetermined amount of fuel, traveling of a vehicle through a predetermined travel distance, and execution of a predetermined number of operation cycle(s). The predetermined prerequisite operational condition may be satisfied when an operational state of the internal combustion engine is a deceleration fuel cut-off state or an idle state.