Abstract: A controller architecture optimized for processing audio and video information in playback systems used for reproducing information stored on optical discs such as CDs and DVDs. The controller uses a unique parallel interface to facilitate the transfer of CD data and DVD data from the controller to a MPEG decoder. The controller also performs servo control operations, data processing and error detection and correction operations for CD data and DVD data, and provides shared memory resources for internal operations of the controller. DVD/CD playback systems incorporating the present invention occupy less real estate, have smaller pin counts, are less complex, and are cheaper to manufacture than conventional playback systems.

Abstract: The present invention provides a method and device for processing servo error signals using a programmable circular linked list to minimize latency. The servo error signals are associated with servo channels. A plurality of data entries are stored in a circular linked list for processing a plurality of servo error signals with one data entry for each servo error channel. Each data entry includes a set of data for processing an associated servo error signal and each set of data includes a time interval that specifies a duration required for processing the associated servo error signal in a digital data format. The time required for converting an analog signal into the digital data format is determined and stored as an ADC conversion time. Then, a data entry is accessed from the circular linked list for processing a servo error signal associated with the data entry. Within the ADC conversion time, the servo error signal is converted into digital data.

Abstract: A circuit for doubling the frequency of a periodic input signal includes an input stage to produce a first signal pulse during a first half of a first cycle of the periodic input signal and a second signal pulse during a second half of the first cycle of the periodic input signal. A reset stage produces a first reset signal that terminates the first signal pulse and a second reset signal that terminates the second signal pulse. The first signal pulse and the second signal pulse form a two cycle output signal during the first cycle of the periodic input signal.

Abstract: A pair of complementary logic gates (A and B) are used to test for faults in a group of electronic components (C1-C3) which provide respective component signals (S1-S3) indicative of their condition. One (A) of the gates ideally generates the logical OR or NOR of the component signals. The other (B) ideally generates their logical AND or NAND. The test procedure involves providing the components with information patterns that would ideally cause all the component signals to go to a logical "0" in one step and to logical "1" in another step. The actual values of the gate output signals (OA and OB) during these two steps are then compared with the respective ideal values to assess the condition of the components.