Abstract: A digital television transmitting system includes a pre-processor, a packet generator, an RS encoder, and a trellis encoder. The pre-processor pre-processes enhanced data by coding the enhanced data for first forward error correction (FEC) and expanding the FEC-coded enhanced data. The packet generator generates first and second enhanced data packets including the pre-processed enhanced data and main data packets and multiplexes the enhanced and main data packets. The first enhanced data packet includes an adaptation field including the pre-processed enhanced data and second enhanced data packet includes a payload region including the pre-processed enhanced data. The RS encoder performs RS encoding on the multiplexed data packets for second forward error correction (FEC), and the trellis encoder performs trellis encoding on the RS-coded data packets.

Abstract: A digital television receiving system includes a first known data detector, a second known data detector, and a selector. The first known data detector detects a location of a first known data sequence in a broadcast signal by calculating a first correlation value between the broadcast signal and a first reference known data sequence. Similarly, the second known data detector detects a location of a second known data sequence in the broadcast signal by calculating a second correlation value between the broadcast signal and a second reference known data sequence. The selector selects the location information detected by one of the first and second known data detectors with a greater correlation value.

Abstract: A digital television receiving system includes a frame encoder, a data randomizing and expanding unit, a group formatter, a block processor, a deinterleaver, and a multiplexer. The frame encoder encodes an enhanced data frame for error correction. The data randomizing and expanding unit randomizes the encoded enhanced data and expands the randomized enhanced data. The group formatter forms a group of enhanced data having head, body, and tail regions and inserts the expanded data and transmission parameters into the body region. The block processor codes the group of enhanced data, and the deinterleaver deinterleaves the coded enhanced data. The packet formatter formats the deinterleaved enhanced data into enhanced data packets.

Abstract: A television transmitting system includes an encoder, a data randomizing and expanding unit, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection. The randomizing and expanding unit randomizes the error-detection-coded data and expands the randomized data. The group formatter forms a group of enhanced data having one or more data regions and inserts the expanded enhanced data into at least one of the regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter generates enhanced data packets.

Abstract: A vestigial sideband (VSB) modulation transmission system and a method for encoding an input signal in the system are disclosed. According to the present invention, the VSB transmission system includes a convolutional encoder for encoding an input signal, a trellis-coded modulation (TCM) encoder for encoding the convolutionally encoded signal, and a signal mapper mapping the trellis-coded signal to generate a corresponding output signal. Different types of the convolutional encoders are explored, and the experimental results showing the performances of the VSB systems incorporating each type of encoders reveals that a reliable data transmission can be achieved even at a lower input signal to noise ratio when a convolutional encoder is used as an error-correcting encoder in a VSB system.

Abstract: A channel equalizer includes a first transformer, an estimator, an average calculator, a second transformer, a coefficient calculator, a compensator, and a third transformer. The first transformer converts normal data into frequency domain data, where a known data sequence is periodically repeated in the normal data. The estimator estimates channel impulse responses (CIR) during known data intervals adjacent to each normal data block. The average calculator calculates an average value of the CIRs. The second transformer converts the average value into frequency domain data. The coefficient calculator calculates equalization coefficients using the average value, and the compensator compensates channel distortion of each normal data block using the coefficients. The third transformer converts the compensated data block into time domain data.

Abstract: A DTV transmitting system includes two pre-processors. The first pre-processor codes high-priority enhanced data for forward error correction (FEC) and expands the FEC-coded data. The second pre-processor codes low-priority enhanced data for FEC and expands the FEC-coded low-priority enhanced data. The DTV transmitting system further includes a data formatter generating enhanced data packets including the pre-processed data, a multiplexer multiplexing the enhanced data packets with main data packets, an RS encoder RS-coding the multiplexed data packets, a data interleaver interleaving the RS-coded data packets, and a block processor which codes each block of enhanced data in the interleaved enhanced data packets and bypasses the interleaved main data packets.

Abstract: A channel equalizer includes an overlap unit, an estimator, a calculator, a compensator, and a save unit. The overlap unit overlaps a group of data packets in a broadcast signal. The group data packets include a head, a body, and a tail, and a known data sequence is periodically included in the body. The estimator estimates a CIR of each data region the body using the known data sequence, and it further estimates CIRs of data regions in the head or tail using the CIRs obtained for the data regions in the body. The calculator calculates equalization coefficients based on the CIRs estimated by the estimator, and the compensator compensates channel distortion of the overlapped data using the equalization coefficients. The save unit saves the compensated data.

Abstract: An electrostatic discharge protection circuit protects the internal circuits of a semiconductor. The electrostatic discharge protection circuit includes a first electrostatic protection unit connected to a power source supply pad. The first electrostatic protection unit discharges an ESD current into the power source supply pad when an ESD is introduced into the input/output pad, and generates a first driving voltage by utilizing the ESD current flow through a voltage-drop unit. A driver driven by the first driving voltage generates a second driving voltage by an ESD current. A second electrostatic protection unit discharges the introduced ESD current into the power source supply pad by the second driving voltage such that a voltage applied to a gate of the first NMOS transistor is reduced.

Abstract: A DTV transmitter includes an encapsulation unit which encapsulates enhanced data having an internet protocol (IP) format into a plurality of addressable sections. The encapsulation unit inserts burst time information into each addressable section. The DTV transmitter further includes a first multiplexer multiplexing the encapsulated enhanced data with program and system information, a pre-processor pre-processing the multiplexed enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting the known data into the enhanced data packets, and a second multiplexer generating one or more bursts of data by multiplexing the enhanced data packets.

Abstract: A DTV receiver includes a tuner tuning to a channel to receive a broadcast signal, and a demodulator demodulating the broadcast signal. The receiver further includes a first decoder which decodes main and enhanced data included in the demodulated signal by calculating soft decision values for the enhanced data and hard decision values for the main data. The receiver further includes a second decoder for decoding the main and enhanced data for first forward error correction, and a third decoder for decoding the FEC-decoded enhanced data for second forward error correction.

Abstract: A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed enhanced data, and a multiplexer multiplexing the enhanced data packets with main data packets. The transmitter further includes an RS encoder RS-coding the multiplexed packets by adding systematic RS parity data to each main data packet and by adding non-systematic RS parity place holders to each enhanced data packet, and a data interleaver interleaving the RS-coded packets. The non-systematic RS parity place holders are placed after the enhanced data within each interleaved enhanced data packet, and a sequence of known data place holders is periodically included in the interleaved enhanced data packets.

Abstract: A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting known data place holders to the data packets, and a multiplexer multiplexing the enhanced data packets with main data packets. It further includes an RS encoder which RS-codes the multiplexed data packets, and a data interleaver which interleaves the RS-coded data packets. The RS encoder adds systematic RS parity data to each main data packet and adds non-systematic RS parity place holders to each enhanced data packet. The RS encoder adds the RS parity place holders such that the RS parity place holders are placed after the enhanced data within each interleaved enhanced data packet.

Abstract: A DTV transmitter includes a pre-processor expanding original enhanced data, a data formatter generating enhanced data packets including the expanded enhanced data and inserting known data place holders into the data packets, a multiplexer multiplexing the enhanced data packets with main data packets including main data, and an RS encoder adding systematic RS parity data to each main data packet and adding non-systematic RS parity data holders to each enhanced data packet. It further includes a data interleaver interleaving the RS-coded data packets, a known data generator generating know data symbols, a converter converting the interleaved data packet into symbols, and a symbol processor processing the converted symbols. The symbol processor removes symbols representing the null data, encodes symbols representing the original enhanced data at a rate of N/M, and replaces symbols representing the know data place holders with known data symbols.

Abstract: A VSB reception system includes a sequence generator for decoding a symbol corresponding to the supplemental data and generating a predefined sequence included in the supplemental data at VSB transmission system. The reception system also includes a modified legacy VSB receiver for processing the data received from the VSB transmission system in a reverse order of the VSB transmission system by using the sequence, and a demultiplexer for demultiplexing the data from the modified legacy VSB receiver into the MPEG data and the supplemental data. The VSB reception system also includes a supplemental data processor for processing the supplemental data segment from the demultiplexer in a reverse order of the transmission system, to obtain the supplemental data, thereby carrying out the slicer prediction, decoding, and symbol decision more accurately by using the predefined sequence, to improve a performance.

Abstract: A VSB reception system includes a sequence generator for decoding a symbol corresponding to the supplemental data and generating a predefined sequence included in the supplemental data at VSB transmission system. The reception system also includes a modified legacy VSB receiver for processing the data received from the VSB transmission system in a reverse order of the VSB transmission system by using the sequence, and a demultiplexer for demultiplexing the data from the modified legacy VSB receiver into the MPEG data and the supplemental data. The VSB reception system also includes a supplemental data processor for processing the supplemental data segment from the demultiplexer in a reverse order of the transmission system, to obtain the supplemental data, thereby carrying out the slicer prediction, decoding, and symbol derision more accurately by using the predefined sequence, to improve a performance.

Abstract: A DTV transmitter includes a pre-processor expanding original enhanced data, a data formatter generating enhanced data packets and inserting known data into the data packets, a multiplexer multiplexing the enhanced data packets with main data packets, a data randomizer randomizing the multiplexed data packets, an RS encoder RS-coding the randomized data packets, and a data interleaver interleaving the RS-coded data packets. The DTV transmitter further includes a byte-symbol converter converting the interleaved data packets into corresponding symbols, and a symbol processor encoding symbols representing the original enhanced data.

Abstract: A VSB reception system includes a sequence generator for decoding a symbol corresponding to the supplemental data and generating a predefined sequence included in the supplemental data at VSB transmission system. The reception system also includes a modified legacy VSB receiver for processing the data received from the VSB transmission system in a reverse order of the VSB transmission system by using the sequence, and a demultiplexer for demultiplexing the data from the modified legacy VSB receiver into the MPEG data and the supplemental data. The VSB reception system also includes a supplemental data processor for processing the supplemental data segment from the demultiplexer in a reverse order of the transmission system, to obtain the supplemental data, thereby carrying out the slicer prediction, decoding, and symbol decision more accurately by using the predefined sequence, to improve a performance.

Abstract: A digital television (DTV) transmitter/receiver and a method of processing data in the DTV transmitter/receiver are disclosed. In the DTV transmitter, a pre-processor pre-processes the enhanced data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded enhanced data. A data formatter generates enhanced data packets including the pre-processed enhanced data and inserts known data to at least one of the enhanced data packets. A first multiplexer multiplexes the enhanced data packets with main data packets including the main data. And, an RS encoder RS-codes the multiplexed main and enhanced data packets, the RS encoder adding systematic parity data to each main data packet and adding RS parity place holders to each enhanced data packet. Herein, the RS encoder may insert non-systematic RS parity data or null data into the RS parity place holders included in each enhanced data packet.

Abstract: A DTV receiver includes a tuner, a demodulator, a channel equalizer, a sequence detector, and a burst controller. The tuner receives a DTV signal having main data and at least one burst of enhanced data. The demodulator demodulates the DTV signal by performing carrier and time recovery and the channel equalizer equalizes the demodulated signal. The sequence detector detects one or more known data sequences from any one of the received signal and the demodulated signal. The demodulator and the channel equalizer use the detected known data sequences when performing the carrier and timing recover and the channel-equalization, respectively. Lastly, the burst controller supplies power to the tuner, the demodulator, the channel equalizer, and the data detector only during a burst time for each burst of enhanced data for efficient power consumption.