Patents by Inventor Kosuke Tatsumura

Kosuke Tatsumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120139007
    Abstract: According to one embodiment, a fabrication method of a semiconductor device comprising forming a dummy gate with a gate length direction set to a [111] direction perpendicular to a [110] direction on a surface of a supporting substrate having Si1-xGex (0?x<0.5) with a crystal orientation perpendicular to the surface set to the [110] direction on the surface, forming source/drain regions and forming insulating films on side portions of the dummy gate. Next, the dummy gate is etched with using the insulating films as a mask, and a surface portion of the substrate between the source/drain regions is further etched. Next, a channel region formed of a III-V group semiconductor or Ge is grown between the source/drain regions by using the edge portions of the source/drain regions as seeds. Then, a gate electrode is formed above the channel region via a gate insulating film.
    Type: Application
    Filed: January 5, 2012
    Publication date: June 7, 2012
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita
  • Publication number: 20120117354
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 10, 2012
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Publication number: 20110246451
    Abstract: According to one embodiment, a storage device includes an interface, a first and second memory blocks and a controller. The interface receives a content search request. The first memory block stores files and inverted files corresponding to contents included in the files. The second memory block stores a file search table. The controller creates the inverted file for each content included in the files and stores IDs of the files including the content in the inverted file. The controller obtains, by search of the content, a corresponding inverted file from the inverted files stored in the first memory block and stores, in the file search table, the IDs of the files included in the obtained inverted file. The controller outputs the IDs of the files stored in the file search table from the interface as a search result for the content search request.
    Type: Application
    Filed: September 23, 2010
    Publication date: October 6, 2011
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita
  • Patent number: 7968956
    Abstract: A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Tatsumura, Masakazu Goto, Reika Ichihara, Masato Koyama, Shigeru Kawanaka, Kazuaki Nakajima