Patents by Inventor Kosuke Yoshida
Kosuke Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12272125Abstract: A learning device performs learning a facial recognition model so as to further reduce a triplet loss that uses a first facial image, a second facial image that is a candidate for an adversarial example of a same person as the first facial image, and a third facial image that is a candidate for an adversarial example of a different person than the first facial image.Type: GrantFiled: January 14, 2020Date of Patent: April 8, 2025Assignee: NEC CORPORATIONInventor: Kosuke Yoshida
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Publication number: 20250029838Abstract: A semiconductor apparatus includes a flat portion disposed in a predetermined region containing a central depth position of a semiconductor substrate, between a fist peak disposed in an upper surface side of the semiconductor substrate and a second peak disposed in a lower surface side of the semiconductor substrate, and having a substantially flat concentration higher than a bulk donor concentration in a donor concentration distribution in a depth direction of a semiconductor substrate. The entire oxygen chemical concentration between the first peak and the second peak ranges from 3×1015 atoms/cm3 to 2×1018 atoms/cm3.Type: ApplicationFiled: October 2, 2024Publication date: January 23, 2025Inventors: Kosuke YOSHIDA, Takashi YOSHIMURA, Hiroshi TAKISHITA, Misaki UCHIDA, Michio NEMOTO, Nao SUGANUMA, Motoyoshi KUBOUCHI
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Patent number: 12190239Abstract: A model building apparatus includes: a building unit that builds a generation model that outputs an adversarial example, which causes misclassification by a learned model, when a source sample is entered into the generation model; and a calculating unit that calculates a first evaluation value and a second evaluation value, wherein the first evaluation value is smaller as a difference is smaller between an actual visual feature of the adversarial example outputted from the generation model and a target visual feature of the adversarial example that are set to be different from a visual feature of the source sample, and the second evaluation value is smaller as there is a higher possibility that the learned model misclassifies the adversarial example outputted from the generation model. The building unit builds the generation model by updating the generation model such that an index value based on the first and second evaluation values is smaller.Type: GrantFiled: February 12, 2019Date of Patent: January 7, 2025Assignee: NEC CORPORATIONInventors: Kazuya Kakizaki, Kosuke Yoshida
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Patent number: 12157457Abstract: An oil dilution inhibiting apparatus is configured to inhibit oil dilution caused by mixture of fuel into engine oil. The oil dilution inhibiting apparatus includes a control unit. The control unit is configured to estimate friction of an engine and determine that the oil dilution occurs when the friction of the engine is decreased to a value lower than or equal to a predetermined threshold value to perform control so that the engine is operated at a higher speed.Type: GrantFiled: September 1, 2023Date of Patent: December 3, 2024Assignee: SUBARU CORPORATIONInventors: Naonori Hagiwara, Yuuki Ito, Kenu Takahashi, Yuki Sugie, Kosuke Yoshida, Yuuma Suzuki, Shogo Watanabe
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Publication number: 20240352532Abstract: Disclosed herein are methods for predicting the clinical or disease outcome of a subject with a disease. The methods for generating an index to predict the disease outcome are also provided. The methods comprise procedures for measuring miRNA levels in a cell-free sample of a subject. The compositions for practicing the same are further provided.Type: ApplicationFiled: March 27, 2024Publication date: October 24, 2024Inventors: Akira YOKOI, Kosuke YOSHIDA, Hiroaki KAJIYAMA, Tomoyasu KATO, Yusuke YAMAMOTO
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Patent number: 12119227Abstract: Provided is a semiconductor apparatus including: a first peak of a hydrogen chemical concentration disposed on the lower surface side of the semiconductor substrate; and a flat portion disposed on the upper surface side of the semiconductor substrate with respect to the first peak, containing a hydrogen donor, and having a substantially (almost) flat donor concentration distribution in a depth direction. An oxygen contribution ratio indicating a ratio of an oxygen chemical concentration contributing to generation of the hydrogen donor in the oxygen chemical concentration of the oxygen ranges from 1×10?5 to 7×10?4. A concentration of the oxygen contributing to generation of the hydrogen donor in the flat portion is lower than the hydrogen chemical concentration. A hydrogen donor concentration in the flat portion ranges from 2×1012/cm3 to 5×1014/cm3.Type: GrantFiled: November 24, 2021Date of Patent: October 15, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kosuke Yoshida, Takashi Yoshimura, Hiroshi Takishita, Misaki Uchida, Michio Nemoto, Nao Suganuma, Motoyoshi Kubouchi
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Patent number: 12009268Abstract: A semiconductor device includes trench portions arrayed in a first direction on an upper surface side of a semiconductor substrate, a first conductivity type lower surface region provided in a part of a lower surface of the semiconductor substrate, a second conductivity type base region provided on the upper surface side, a first conductivity type first region disposed between the base region and the lower surface region, a first conductivity type upper surface region provided on an upper surface of the semiconductor substrate, and a second conductivity type bottom region disposed continuously in the first direction to be in contact with bottom portions of the trench portions. In a cross section along the first direction and perpendicular to the upper and lower surfaces and passing through the lower surface region, one end portion of the bottom region in the first direction locates directly above the lower surface region.Type: GrantFiled: July 14, 2023Date of Patent: June 11, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motoyoshi Kubouchi, Kosuke Yoshida, Soichi Yoshida, Koh Yoshikawa, Nao Suganuma
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Patent number: 11989013Abstract: An abnormality detection apparatus (200) includes storage means (210) for storing a learned self-encoder (211) including predetermined number of two or more of elements as input layers, extraction means (220) for extracting a target data group of a predetermined period including data pieces from time series data measured by one or more sensors, the number of the data pieces being the predetermined number, conversion means (230) for converting the target data group into multi-dimensional vector data including the predetermined number of elements, identifying means (240) for identifying a time period in which there may be a cause of an abnormality from the predetermined period based on a difference between output vector data having the predetermined number of elements obtained by inputting the multi-dimensional vector data to the self-encoder (211) and the multi-dimensional vector data, and output means (250) for outputting abnormality detection information including the identified time period.Type: GrantFiled: January 18, 2019Date of Patent: May 21, 2024Assignee: NEC CORPORATIONInventor: Kosuke Yoshida
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Publication number: 20240128362Abstract: Provided is a semiconductor device comprising: a plurality of trench portions include a gate trench portion and a dummy trench portion; a first lower end region of a second conductivity type that is provided to be in contact with lower ends of two or more trench portions which include the gate trench portion; a well region of a second conductivity type that is arranged in a different location from the first lower end region in a top view, and a second lower end region of a second conductivity type that is provided between the first lower end region and the well region in a top view being separated from the first lower end region and the well region, and provided to be in contact with lower ends of one or more trench portions including the gate trench portion.Type: ApplicationFiled: December 18, 2023Publication date: April 18, 2024Inventors: Yosuke SAKURAI, Seiji NOGUCHI, Kosuke YOSHIDA, Ryutaro HAMASAKI, Takuya YAMADA
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Publication number: 20240120413Abstract: Provided is a semiconductor device comprising: a plurality of trench portions; a first lower end region of a second conductivity type that is provided to be in contact with lower ends of two or more trench portions which include the gate trench portion; a well region of the second conductivity type that is arranged in a different location from the first lower end region in a top view, and a second lower end region of the second conductivity type that is provided between the first lower end region and the well region in a top view being separated from the first lower end region and the well region, and provided to be in contact with lower ends of one or more trench portions including the gate trench portion.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Inventors: Yosuke SAKURAI, Seiji NOGUCHI, Kosuke YOSHIDA, Ryutaro HAMASAKI, Takuya YAMADA
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Publication number: 20240083407Abstract: An oil dilution inhibiting apparatus is configured to inhibit oil dilution caused by mixture of fuel into engine oil. The oil dilution inhibiting apparatus includes a control unit. The control unit is configured to estimate friction of an engine and determine that the oil dilution occurs when the friction of the engine is decreased to a value lower than or equal to a predetermined threshold value to perform control so that the engine is operated at a higher speed.Type: ApplicationFiled: September 1, 2023Publication date: March 14, 2024Inventors: Naonori HAGIWARA, Yuuki ITO, Kenu TAKAHASHI, Yuki SUGIE, Kosuke YOSHIDA, Yuuma SUZUKI, Shogo WATANABE
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Patent number: 11899793Abstract: An information processing apparatus (2000) classifies each event that occurred in a target apparatus to be determined (10) either as an event (event of a first class) that also occurs in a standard apparatus (20) or as an event (event of a second class) that does not occur in the standard apparatus (20). Herein, a first model used for a determination with respect to an event that also occurs in the standard apparatus (20) and a second model used for a determination with respect to an event that does not occur in the standard apparatus (20) are used as models for determining whether an event that occurs in a target apparatus to be determined (10) is a target for warning. The information processing apparatus (2000) performs learning of the first model using an event of the first class. Further, the information processing apparatus (2000) performs learning of the second model using an event of the second class.Type: GrantFiled: March 1, 2018Date of Patent: February 13, 2024Assignee: NEC CORPORATIONInventors: Kazuhiko Isoyama, Yoshiaki Sakae, Jun Nishioka, Etsuko Ichihara, Kosuke Yoshida
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Publication number: 20230369137Abstract: A semiconductor device includes trench portions arrayed in a first direction on an upper surface side of a semiconductor substrate, a first conductivity type lower surface region provided in a part of a lower surface of the semiconductor substrate, a second conductivity type base region provided on the upper surface side, a first conductivity type first region disposed between the base region and the lower surface region, a first conductivity type upper surface region provided on an upper surface of the semiconductor substrate, and a second conductivity type bottom region disposed continuously in the first direction to be in contact with bottom portions of the trench portions. In a cross section along the first direction and perpendicular to the upper and lower surfaces and passing through the lower surface region, one end portion of the bottom region in the first direction locates directly above the lower surface region.Type: ApplicationFiled: July 14, 2023Publication date: November 16, 2023Inventors: Motoyoshi KUBOUCHI, Kosuke YOSHIDA, Soichi YOSHIDA, Koh YOSHIKAWA, Nao SUGANUMA
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Patent number: 11742249Abstract: A fabrication method for a semiconductor device includes measuring a thickness of a semiconductor substrate in which a bulk donor of a first conductivity type is entirely distributed, adjusting an implantation condition in accordance with the thickness of the semiconductor substrate and implanting hydrogen ions from a lower surface of the semiconductor substrate to an upper surface side of the semiconductor substrate, and annealing the semiconductor substrate and forming, in a passage region through which the hydrogen ions have passed, a first high concentration region of the first conductivity type in which a donor concentration is higher than a doping concentration of the bulk donor.Type: GrantFiled: September 5, 2022Date of Patent: August 29, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motoyoshi Kubouchi, Kosuke Yoshida, Soichi Yoshida, Koh Yoshikawa, Nao Suganuma
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Patent number: 11727059Abstract: To enable a user to easily recognize temporal order of elements included in a retrieval sentence, a retrieval sentence utilization device 10 includes: a retrieval sentence division unit 11 for dividing a retrieval sentence into a plurality of retrieval contents each of which includes an event; and a directed graph generation unit 12 for generating, from each of the retrieval contents, a subtree in which the event is an edge and a source of the event and an object of the event are nodes, and integrating a plurality of subtrees generated from the retrieval contents to generate a directed graph, wherein the directed graph generation unit 12 places the plurality of subtrees in the directed graph according to occurrence order of events corresponding to the plurality of subtrees.Type: GrantFiled: March 14, 2018Date of Patent: August 15, 2023Assignee: NEC CORPORATIONInventors: Jun Nishioka, Yoshiaki Sakae, Kazuhiko Isoyama, Etsuko Ichihara, Kosuke Yoshida
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Patent number: 11631666Abstract: There is provided a semiconductor device including: an emitter region of a first conductivity type, a contact region of a second conductivity type, provided on the front surface side of the semiconductor substrate; one or more first trench portions which are electrically connected to a gate electrode and are in contact with emitter regions; a second trench portion which is adjacent to one of the one or more first trench portions, is electrically connected to the gate electrode, is in contact with the contact region of the second conductivity type, and is not in contact with the emitter region; and a dummy trench portion which is adjacent to one of the one or more first trench portions and is electrically connected to an emitter electrode, in which the contact region in contact with the second trench portion is in contact with the emitter electrode.Type: GrantFiled: March 1, 2022Date of Patent: April 18, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventor: Kosuke Yoshida
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Publication number: 20230081512Abstract: Provided is a semiconductor device including a semiconductor substrate having a first dopant of a first conductivity type and a second dopant of a second conductivity type, both the first dopant and the second dopant being distributed in an entire part of the semiconductor substrate, the semiconductor substrate including a drift region of the first conductivity type, a dielectric film provided on an upper surface of the semiconductor substrate, a high concentration region of the first conductivity type provided in contact with the dielectric film below the dielectric film and having a higher doping concentration than the drift region, and a fall off region that is provided in contact with the dielectric film below the dielectric film and in which a concentration of the dopant of the second conductivity type decreases toward the dielectric film.Type: ApplicationFiled: August 22, 2022Publication date: March 16, 2023Inventors: Koh YOSHIKAWA, Kosuke YOSHIDA, Nao SUGANUMA
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Publication number: 20230085529Abstract: Provided is a semiconductor device including: a semiconductor substrate having a drift region of a first conductivity type; an active portion, in which at least one of a transistor portion and a diode portion is provided, in the semiconductor substrate; and an edge termination structure portion provided farther outward than the active portion in the semiconductor substrate, wherein the edge termination structure portion has a plurality of guard rings of a second conductivity type provided in contact with an upper surface of the semiconductor substrate, and an embedded dielectric film arranged between two guard rings and at least partially embedded in the semiconductor substrate, and the guard rings are provided up to a position below the embedded dielectric film.Type: ApplicationFiled: August 22, 2022Publication date: March 16, 2023Inventors: Kosuke YOSHIDA, Koh Yoshikawa, Nao Suganuma
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Publication number: 20230040096Abstract: A fabrication method for a semiconductor device includes measuring a thickness of a semiconductor substrate in which a bulk donor of a first conductivity type is entirely distributed, adjusting an implantation condition in accordance with the thickness of the semiconductor substrate and implanting hydrogen ions from a lower surface of the semiconductor substrate to an upper surface side of the semiconductor substrate, and annealing the semiconductor substrate and forming, in a passage region through which the hydrogen ions have passed, a first high concentration region of the first conductivity type in which a donor concentration is higher than a doping concentration of the bulk donor.Type: ApplicationFiled: September 5, 2022Publication date: February 9, 2023Inventors: Motoyoshi KUBOUCHI, Kosuke YOSHIDA, Soichi YOSHIDA, Koh YOSHIKAWA, Nao SUGANUMA
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Publication number: 20230029988Abstract: A learning device performs learning a facial recognition model so as to further reduce a triplet loss that uses a first facial image, a second facial image that is a candidate for an adversarial example of a same person as the first facial image, and a third facial image that is a candidate for an adversarial example of a different person than the first facial image.Type: ApplicationFiled: January 14, 2020Publication date: February 2, 2023Applicant: NEC CorporationInventor: Kosuke YOSHIDA