Patents by Inventor Kota V R M Murali
Kota V R M Murali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10418505Abstract: A method including installing solar pods at varying heights on a tower, where a size of each of the solar pods is inversely related its installation height on the tower, each of the solar pods including a transparent ovoid enclosure symmetrical about an axis, and a reflector and a solar cell both contained within the transparent ovoid enclosure, the solar cell positioned at a common focal point of the reflector such that substantially all light reflected by the reflector is directed at the solar cell.Type: GrantFiled: May 18, 2017Date of Patent: September 17, 2019Assignee: International Business Machines CorporationInventors: Aveek N. Chatterjee, Kota V. R. M. Murali, Ninad D. Sathaye, Rajesh Sathiyanarayanan
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Patent number: 10373942Abstract: A method of forming a SRAM semiconductor device with reduced area layout and a resulting device are provided. Embodiments include forming a first field effect transistor (FET) over a substrate; forming an insulating material over the first FET; forming a second FET over the insulating material; and patterning the first FET, insulating material and second FET to form fins over the substrate.Type: GrantFiled: December 1, 2017Date of Patent: August 6, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ram Asra, Mohit Bajaj, Edward Nowak, Kota V. R. M. Murali
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Publication number: 20190172822Abstract: A method of forming a SRAM semiconductor device with reduced area layout and a resulting device are provided. Embodiments include forming a first field effect transistor (FET) over a substrate; forming an insulating material over the first FET; forming a second FET over the insulating material; and patterning the first FET, insulating material and second FET to form fins over the substrate.Type: ApplicationFiled: December 1, 2017Publication date: June 6, 2019Inventors: Ram ASRA, Mohit BAJAJ, Edward NOWAK, Kota V. R. M. MURALI
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Patent number: 10163716Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: GrantFiled: October 25, 2017Date of Patent: December 25, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
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Patent number: 10164027Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: GrantFiled: October 26, 2017Date of Patent: December 25, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
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Publication number: 20180130655Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: ApplicationFiled: October 25, 2017Publication date: May 10, 2018Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
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Patent number: 9911598Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: GrantFiled: January 12, 2017Date of Patent: March 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
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Publication number: 20180053828Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: ApplicationFiled: October 26, 2017Publication date: February 22, 2018Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
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Patent number: 9876084Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: GrantFiled: March 29, 2016Date of Patent: January 23, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
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Publication number: 20170256664Abstract: A method including installing solar pods at varying heights on a tower, where a size of each of the solar pods is inversely related its installation height on the tower, each of the solar pods including a transparent ovoid enclosure symmetrical about an axis, and a reflector and a solar cell both contained within the transparent ovoid enclosure, the solar cell positioned at a common focal point of the reflector such that substantially all light reflected by the reflector is directed at the solar cell.Type: ApplicationFiled: May 18, 2017Publication date: September 7, 2017Inventors: Aveek N. Chatterjee, Kota V.R.M. Murali, Ninad D. Sathaye, Rajesh Sathiyanarayanan
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Patent number: 9705079Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: GrantFiled: November 4, 2016Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Patent number: 9705021Abstract: A solar pod system, comprising of an oval transparent enclosure. The oval transparent enclosure encapsulates a circular paraboloidal reflector mounted on solar cell. The solar cell extends over the circular parabolic reflector to place the focus of the paraboloidal reflector on the solar cell, whereby the solar cell receives light reflected by the circular parabolic reflector.Type: GrantFiled: October 30, 2014Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Aveek N. Chatterjee, Kota V. R. M. Murali, Ninad D. Sathaye, Rajesh Sathiyanarayanan
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Publication number: 20170194467Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: ApplicationFiled: January 12, 2017Publication date: July 6, 2017Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
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Patent number: 9680096Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: GrantFiled: July 15, 2016Date of Patent: June 13, 2017Assignee: International Business Machines CorporationInventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Patent number: 9671810Abstract: A system and method for providing power is disclosed. A variable direct current (DC) power source provides a variable DC voltage. A configurator dynamically converts the variable DC voltage to a selected DC voltage to provide the power. A set of switches combines the solar voltage with a substantially constant DC voltage. A control unit controls the set of switches and the configurator to provide the combined voltages at a selected voltage level.Type: GrantFiled: October 26, 2012Date of Patent: June 6, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shankar Km, William P. Kostenko, Anand D. Meshram, Kota V R M Murali, Roger R. Schmidt
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Patent number: 9654414Abstract: A method for scheduling cost efficient data center load distribution is described. The method includes receiving a task to be performed by computing resources within a set of data centers. The method further includes determining, all available data centers to perform the task. The method further includes determining lowest computing cost task schedule from available data centers. The method further includes scheduling the task to be completed at an available data center with the lowest cost computing.Type: GrantFiled: September 18, 2014Date of Patent: May 16, 2017Assignee: International Business Machines CorporationInventors: Aveek N. Chatterjee, Hendrik F. Hamann, Shankar Km, Siyuan Lu, Kota V. R. M. Murali
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Patent number: 9647210Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: GrantFiled: March 23, 2015Date of Patent: May 9, 2017Assignee: International Business Machines CorporationInventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Patent number: 9613867Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: GrantFiled: March 29, 2016Date of Patent: April 4, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
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Patent number: 9589635Abstract: A device that includes a semiconductor device and a contact electrode with a first side that is opposite a second side. The first side abuts the semiconductor device. The contact electrode has a stoichiometry that varies from the first side to the second side. The stoichiometry of the first side inhibits the diffusion of metal from the semiconductor device into the first contact electrode.Type: GrantFiled: December 11, 2014Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Mohit Bajaj, Geoffrey W. Burr, Kota V. R. M. Murali, Rajan K. Pandey, Rajesh Sathiyanarayanan, Kumar R. Virwani
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Publication number: 20170062594Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: ApplicationFiled: March 29, 2016Publication date: March 2, 2017Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK