Patents by Inventor Kota V R M Murali
Kota V R M Murali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170062234Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: ApplicationFiled: March 29, 2016Publication date: March 2, 2017Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
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Publication number: 20170047515Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: ApplicationFiled: November 4, 2016Publication date: February 16, 2017Inventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Patent number: 9552852Abstract: Some embodiments of the present invention may include one, or more, of the following features, characteristics or advantages: (i) latch device including multiple Ecrit material regions all electrically connected to a common terminal (sometimes structured and shaped in the form of a storage plate conductor); (ii) bi-stable three-terminal latch device using two Ecrit property regions; (iii) three-terminal, two-Ecrit-region latch device where, for each Ecrit region, (Vdd?Vss) divided by (region thickness, dn) is greater than the region's Ecrit value; or (iv) use of multiple Ecrit material region latch devices to provide data storage instrumentality in a static memory device.Type: GrantFiled: November 6, 2014Date of Patent: January 24, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Brent A. Anderson, Kota V. R. M. Murali, Edward J. Nowak
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Patent number: 9508930Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: GrantFiled: April 19, 2016Date of Patent: November 29, 2016Assignee: International Business Machines CorporationInventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Publication number: 20160315254Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: ApplicationFiled: July 15, 2016Publication date: October 27, 2016Inventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Publication number: 20160284870Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: ApplicationFiled: March 23, 2015Publication date: September 29, 2016Inventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Publication number: 20160284995Abstract: The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.Type: ApplicationFiled: April 19, 2016Publication date: September 29, 2016Inventors: Mohit Bajaj, Arpan K. Deb, Aniruddha Konar, Kota V. R. M. Murali, Rajan K. Pandey, Kumar R. Virwani
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Patent number: 9419115Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.Type: GrantFiled: October 6, 2015Date of Patent: August 16, 2016Assignee: International Business Machines CorporationInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Kota V. R. M. Murali, Edward J. Nowak
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Patent number: 9419016Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.Type: GrantFiled: November 10, 2014Date of Patent: August 16, 2016Assignee: International Business Machines CorporationInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Kota V. R. M. Murali, Edward J. Nowak
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Patent number: 9389632Abstract: A system and method for providing power is disclosed. A variable direct current (DC) power source provides a variable DC voltage. A configurator dynamically converts the variable DC voltage to a selected DC voltage to provide the power. A set of switches combines the solar voltage with a substantially constant DC voltage. A control unit controls the set of switches and the configurator to provide the combined voltages at a selected voltage level.Type: GrantFiled: March 8, 2013Date of Patent: July 12, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shankar Km, William P. Kostenko, Anand D. Meshram, Kota V R M Murali, Roger R. Schmidt
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Patent number: 9379253Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.Type: GrantFiled: August 27, 2015Date of Patent: June 28, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
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Publication number: 20160172420Abstract: A device that includes a semiconductor device and a contact electrode with a first side that is opposite a second side. The first side abuts the semiconductor device. The contact electrode has a stoichiometry that varies from the first side to the second side. The stoichiometry of the first side inhibits the diffusion of metal from the semiconductor device into the first contact electrode.Type: ApplicationFiled: December 11, 2014Publication date: June 16, 2016Inventors: Mohit Bajaj, Geoffrey W. Burr, Kota V.R.M. Murali, Rajan K. Pandey, Rajesh Sathiyanarayanan, Kumar R. Virwani
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Publication number: 20160133303Abstract: Some embodiments of the present invention may include one, or more, of the following features, characteristics or advantages: (i) latch device including multiple Ecrit material regions all electrically connected to a common terminal (sometimes structured and shaped in the form of a storage plate conductor); (ii) bi-stable three-terminal latch device using two Ecrit property regions; (iii) three-terminal, two-Ecrit-region latch device where, for each Ecrit region, (Vdd?Vss) divided by (region thickness, dn) is greater than the region's Ecrit value; or (iv) use of multiple Ecrit material region latch devices to provide data storage instrumentality in a static memory device.Type: ApplicationFiled: November 6, 2014Publication date: May 12, 2016Inventors: Brent A. Anderson, Kota V.R.M. Murali, Edward J. Nowak
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Publication number: 20160133648Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.Type: ApplicationFiled: November 10, 2014Publication date: May 12, 2016Inventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Kota V.R.M. Murali, Edward J. Nowak
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Publication number: 20160133730Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.Type: ApplicationFiled: October 6, 2015Publication date: May 12, 2016Inventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Kota V.R.M. Murali, Edward J. Nowak
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Publication number: 20160126393Abstract: A solar pod system, comprising of an oval transparent enclosure. The oval transparent enclosure encapsulates a circular paraboloidal reflector mounted on solar cell. The solar cell extends over the circular parabolic reflector to place the focus of the paraboloidal reflector on the solar cell, whereby the solar cell receives light reflected by the circular parabolic reflector.Type: ApplicationFiled: October 30, 2014Publication date: May 5, 2016Inventors: Aveek N. Chatterjee, Kota V. R. M. Murali, Ninad D. Sathaye, Rajesh Sathiyanarayanan
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Publication number: 20160087909Abstract: A method for scheduling cost efficient data center load distribution is described. The method includes receiving a task to be performed by computing resources within a set of data centers. The method further includes determining, all available data centers to perform the task. The method further includes determining lowest computing cost task schedule from available data centers. The method further includes scheduling the task to be completed at an available data center with the lowest cost computing.Type: ApplicationFiled: September 18, 2014Publication date: March 24, 2016Inventors: Aveek N. Chatterjee, Hendrik F. Hamann, Shankar Km, Siyuan Lu, Kota V. R. M. Murali
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Patent number: 9170165Abstract: A workfunction modulation-based sensor comprising a field-effect transistor (FET). The FET comprises a substrate, a gate dielectric, a metal gate, a source, a drain, and a layer of sensing material that is electrically connected to the metal gate. An electrical connection that connects to the source of the FET. An electrical connection that connects to the drain of the FET. An electrical connection that connects to the layer of sensing material. An environment that includes an adsorbate gas surrounding, at least a portion of, the layer of sensing material. Wherein the sensing material is adapted to adsorb, at least in part, the adsorbate gas. The amount of adsorbate gas adsorbed on the layer of sensing material modulates the workfunction of the FET such that the degree of adsorbate gas adsorption corresponds to one of the temperature or pressure associated with the environment of the FET.Type: GrantFiled: March 25, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Balaji Jayaraman, Kota V. R. M. Murali, Edward J. Nowak, Ninad D. Sathaye, Rajesh Sathiyanarayanan
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Patent number: 9105498Abstract: A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions.Type: GrantFiled: March 1, 2012Date of Patent: August 11, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mohit Bajaj, Kota V. R. M. Murali, Rahul Nayak, Edward J. Nowak, Rajan K. Pandey
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Patent number: 9068882Abstract: A low power thermal imager is disclosed. In one embodiment, the thermal imager comprises a cross-bar architecture having a plurality of horizontal lines each arranged in a row, a plurality of vertical lines each arranged in a column, and a plurality of cross-points each formed at an intersection between one of the plurality of horizontal lines and one of the plurality of vertical lines; and a plurality of tunnel junction structures each located at one of the plurality cross-points, each tunnel junction structure including a first metal layer disposed over one of the plurality of vertical lines, an insulator layer disposed over the first metal layer, and a second metal layer disposed over the insulator layer and underneath one of the plurality of horizontal lines.Type: GrantFiled: June 11, 2013Date of Patent: June 30, 2015Assignee: International Business Machines CorporationInventors: Kota V R M Murali, Karthik Venkataraman