Patents by Inventor Kouhei Toyotaka
Kouhei Toyotaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10304555Abstract: To provide a semiconductor device having a high aperture ratio and including a capacitor with a high charge capacitance. To provide a semiconductor device with a narrow bezel. A transistor over a substrate; a first conductive film over a surface over which a gate electrode of the transistor is provided; a second conductive film over a surface over which a pair of electrodes of the transistor is provided; and a first light-transmitting conductive film electrically connected to the first conductive film and the second conductive film are included. The second conductive film overlaps the first conductive film with a gate insulating film of the transistor laid between the second conductive film and the first conductive film.Type: GrantFiled: January 19, 2017Date of Patent: May 28, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiroyuki Miyake, Kouhei Toyotaka
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Patent number: 10256255Abstract: A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.Type: GrantFiled: August 17, 2016Date of Patent: April 9, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kouhei Toyotaka, Jun Koyama, Hiroyuki Miyake
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Publication number: 20190088785Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.Type: ApplicationFiled: September 5, 2018Publication date: March 21, 2019Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Hiroyuki MIYAKE, Kei TAKAHASHI, Kouhei TOYOTAKA, Masashi TSUBUKU, Kosei NODA, Hideaki KUWABARA
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Patent number: 10217772Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.Type: GrantFiled: April 23, 2018Date of Patent: February 26, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideaki Shishido, Hiroyuki Miyake, Kouhei Toyotaka, Makoto Kaneyasu
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Patent number: 10217764Abstract: To provide a light-emitting device or an input/output device with little unevenness in display luminance or high reliability and to provide an input/output device with high detection sensitivity, a light-emitting device is configured to include a first substrate, a light-emitting element over the first substrate, a first conductive layer over the light-emitting element, a first insulating layer over the first conductive layer, a second conductive layer over the first insulating layer, and a second substrate over the second conductive layer. The light-emitting element includes a first electrode over the first substrate, a layer containing a light-emitting organic compound over the first electrode, and a second electrode over the layer containing a light-emitting organic compound. The second electrode is electrically connected to the first and second conductive layers. The first conductive layer and the second electrode transmit light emitted from the light-emitting element.Type: GrantFiled: December 27, 2017Date of Patent: February 26, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Daiki Nakamura, Hisao Ikeda, Kouhei Toyotaka
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Publication number: 20190027507Abstract: A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied.Type: ApplicationFiled: September 10, 2018Publication date: January 24, 2019Inventors: Kouhei TOYOTAKA, Kei TAKAHASHI, Hideaki SHISHIDO, Koji KUSUNOKI
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Patent number: 10141053Abstract: To reduce power consumption of a processing device including a processor and a main memory in the processor. The main memory includes not only a volatile memory such as a DRAM but also a nonvolatile memory. The processor monitors access requirements to the main memory. The processor determines on the basis of the monitoring results whether the volatile memory or the nonvolatile memory operates mainly. In the case where the main memory changes from the volatile memory to the nonvolatile memory, part or all of data stored in the volatile memory is backed up to the nonvolatile memory. While the nonvolatile memory operates mainly, supply of power supply voltage to the volatile memory is stopped or power supply voltage to be supplied is lowered.Type: GrantFiled: April 29, 2014Date of Patent: November 27, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kouhei Toyotaka
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Patent number: 10139663Abstract: An input/output device is provided. The input/output device includes a first pixel electrode, a second pixel electrode, a first common electrode, a second common electrode, a liquid crystal, a first insulating film, a second insulating film, and a transistor. The first common electrode can serve as one electrode of a sensor element. The second common electrode can serve as the other electrode of the sensor element. The transistor includes a first gate, a second gate, and a semiconductor layer. The pixel electrode, the common electrodes, and the second gate are positioned on different planes. The second gate contains one or more kinds of metal elements included in the semiconductor layer. The second gate, the pixel electrode, and the common electrodes preferably contain one or more kinds of metal elements included in the semiconductor layer.Type: GrantFiled: May 12, 2016Date of Patent: November 27, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideaki Shishido, Koji Kusunoki, Kouhei Toyotaka, Kazunori Watanabe, Makoto Kaneyasu
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Publication number: 20180308866Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.Type: ApplicationFiled: April 23, 2018Publication date: October 25, 2018Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideaki Shishido, Hiroyuki Miyake, Kouhei Toyotaka, Makoto Kaneyasu
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Patent number: 10103275Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.Type: GrantFiled: May 31, 2017Date of Patent: October 16, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake, Kei Takahashi, Kouhei Toyotaka, Masashi Tsubuku, Kosei Noda, Hideaki Kuwabara
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Patent number: 10083991Abstract: A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied.Type: GrantFiled: December 12, 2016Date of Patent: September 25, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kouhei Toyotaka, Kei Takahashi, Hideaki Shishido, Koji Kusunoki
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Patent number: 10073571Abstract: To increase the detection sensitivity of a touch panel, increase the visibility of a touch panel, provide a bendable touch panel, provide a thin touch panel, or provide a lightweight touch panel. The touch sensor has a first substrate, a first conductive layer, a second conductive layer, and an insulating layer. The first conductive layer includes a region between the first substrate and the second conductive layer. The insulating layer includes a region between the first conductive layer and the second conductive layer. The first conductive layer, the second conductive layer, and the insulating layer form a capacitor. The second conductive layer has an opening. The opening in the second conductive layer and the first conductive layer overlap with each other in a region.Type: GrantFiled: April 21, 2015Date of Patent: September 11, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazunori Watanabe, Hiroyuki Miyake, Yuji Iwaki, Hideaki Shishido, Kouhei Toyotaka, Koji Kusunoki
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Patent number: 10074747Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.Type: GrantFiled: December 8, 2016Date of Patent: September 11, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake, Kei Takahashi, Kouhei Toyotaka, Masashi Tsubuku, Kosei Noda, Hideaki Kuwabara
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Patent number: 10073551Abstract: Provided is a novel display panel which is highly convenient or reliable or a driving method thereof. The display panel includes a first display element, a first conductive film electrically connected to the first display element, a second conductive film having a region overlapping with the first conductive film, an insulating film having a region sandwiched between the second conductive film and the first conductive film, a pixel circuit electrically connected to the second conductive film, and a second display element electrically connected to the pixel circuit. The insulating film has an opening. The second conductive film is electrically connected to the first conductive film in the opening.Type: GrantFiled: August 2, 2016Date of Patent: September 11, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Daisuke Kubota, Kouhei Toyotaka
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Publication number: 20180180951Abstract: A display device having high display quality is provided. In the display device including a plurality of pixels, adjacent pixel electrodes are formed over different insulating layers. Accordingly, when seen in a plan view, the adjacent pixel electrodes can be close to each other without constraints of design rules. Openings (light-emitting regions) of the adjacent pixels can be close to each other, leading to an improvement in graininess of an image. With the use of a step provided between the adjacent pixel electrodes, the resistance of an EL layer across the adjacent pixels can be increased to reduce crosstalk.Type: ApplicationFiled: December 14, 2017Publication date: June 28, 2018Inventor: Kouhei Toyotaka
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Publication number: 20180182834Abstract: A novel display panel that is highly convenient or reliable is provided. The display panel includes a display region, and the display region includes a first group of pixels, a second group of pixels, a third group of pixels, a fourth group of pixels, a first scan line, a second scan line, a first signal line, and a second signal line. The first group of pixels include a first pixel and are arranged in a row direction. The second group of pixels include a second pixel and are arranged in the row direction. The third group of pixels include a first pixel and are arranged in a column direction that intersects the row direction. The fourth group of pixels include a second pixel and are arranged in the column direction. The first signal line is electrically connected to the third group of pixels and the second signal line is electrically connected to the fourth group of pixels.Type: ApplicationFiled: December 26, 2017Publication date: June 28, 2018Inventors: Kouhei Toyotaka, Kei Takahashi, Hideaki Shishido, Shunpei Yamazaki
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Publication number: 20180151144Abstract: A display device that achieves both high-accuracy sensing by a touch sensor unit and smooth input using the touch sensor unit is provided. The display device includes a display unit and the touch sensor unit. The touch sensor unit performs touch sensing operation at a different timing from display image rewriting by the display unit, whereby the high-accuracy sensing can be achieved. The display unit has a function of rewriting a display image only in a region that needs to be rewritten. In the case where the entire display region is not necessarily rewritten, the time for the sensing operation by the touch sensor unit can be lengthened, whereby the smooth input can be achieved.Type: ApplicationFiled: November 21, 2017Publication date: May 31, 2018Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Susumu Kawashima, Kouhei Toyotaka, Kei Takahashi
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Patent number: 9978329Abstract: Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.Type: GrantFiled: October 21, 2016Date of Patent: May 22, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroyuki Miyake, Kouhei Toyotaka
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Publication number: 20180138201Abstract: To provide a light-emitting device or an input/output device with little unevenness in display luminance or high reliability and to provide an input/output device with high detection sensitivity, a light-emitting device is configured to include a first substrate, a light-emitting element over the first substrate, a first conductive layer over the light-emitting element, a first insulating layer over the first conductive layer, a second conductive layer over the first insulating layer, and a second substrate over the second conductive layer. The light-emitting element includes a first electrode over the first substrate, a layer containing a light-emitting organic compound over the first electrode, and a second electrode over the layer containing a light-emitting organic compound. The second electrode is electrically connected to the first and second conductive layers. The first conductive layer and the second electrode transmit light emitted from the light-emitting element.Type: ApplicationFiled: December 27, 2017Publication date: May 17, 2018Inventors: Daiki NAKAMURA, Hisao IKEDA, Kouhei TOYOTAKA
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Publication number: 20180137822Abstract: A display device includes a plurality of pulse output circuits each of which outputs signals to one of the two kinds of scan lines and a plurality of inverted pulse output circuits each of which outputs, to the other of the two kinds of scan lines, inverted or substantially inverted signals of the signals output from the pulse output circuits. Each of the plurality of inverted pulse output circuits operates with at least two kinds of signals used for the operation of the plurality of pulse output circuits. Thus, through current generated in the inverted pulse output circuits can be reduced.Type: ApplicationFiled: January 12, 2018Publication date: May 17, 2018Inventor: Kouhei Toyotaka