Abstract: When, for example, an acceptance processing unit, among several acceptance processing units, performs acceptance processing of a reservation request, whether or not there is availability in resources of a video chat device assigned to the acceptance processing unit is checked, and if there is availability in the resource, the use of the resource is reserved.

Abstract: A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.

Abstract: A memory capable of reducing the memory cell size is provided. In this memory, a first gate electrode of a first selection transistor and a second gate electrode of a second selection transistor are provided integrally with a word line, and arranged to obliquely extend with respect to the longitudinal direction of a first impurity region on a region formed with memory cells and to intersect with the first impurity region on regions formed with the first selection transistor and the second selection transistor in plan view.

Abstract: In a point-to-multipoint system, the first communication processing apparatus generates a signal to inquire of the second communication processing apparatus about languages used in the second terminals and transmits the signal to the second communication processing apparatus. The second communication processing apparatus generates a second signal which includes data indicating the language which is used most in the second terminals and transmits the second signal to the first communication processing apparatus.

Abstract: A memory operable at a high speed is obtained. This memory comprises a plurality of word lines, first transistors each connected to each the plurality of word lines for entering an ON-state through selection of the corresponding word line, a plurality of memory cells including diodes having cathodes connected to the source or drain regions of the first transistors respectively and a data determination portion connected to the drain or source regions of the first transistors for determining data read from a selected memory cell.

Abstract: A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array(1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells(12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell(12). During this access operation, it is performed to apply to the memory cell(12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell(12).

Abstract: The digital broadcast receiving apparatus according to the present invention includes a tuning unit for outputting normal image data for performing a normal reproduction operation corresponding to a user selected channel, a memory unit for outputting background image data for performing a background reproduction operation when the normal reproduction operation cannot be performed, a data selector for receiving the normal image data and the background image data and outputting one of the normal image data and the background image data, and an MPEG video decode unit for decoding image data output by the data selector to generate an image signal. The tuning unit successively receives the respective channel selected in the background independently of the user selection, and stores the background image data corresponding to the respective channels in the memory unit.

Abstract: A memory capable of reducing the memory cell size is provided. This memory comprises a plurality of memory cells including diodes, a plurality of bit lines and an n-type impurity region arranged to intersect with the bit lines for functioning as cathodes of the diodes included in the memory cells and a word line. The n-type impurity region is divided every bit line group formed by a prescribed number of bit lines.

Abstract: A memory allowing reduction of a memory cell size is obtained. This memory comprises a first conductive type first impurity region formed on the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a word line, a plurality of second conductive type second impurity regions formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode, a bit line formed on the semiconductor substrate and connected to the second impurity regions and a wire provided above the bit line and connected to the first impurity region every prescribed interval.

Abstract: A memory capable of suppressing reduction of data determination accuracy is provided. This memory comprises a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor.

Abstract: A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.

Abstract: A semiconductor device capable of improving the accuracy for determining whether a prescribed input potential is higher or lower than a reference potential is obtained. This semiconductor device comprises first capacitance means and second capacitance means having different ON- and OFF-state capacitances. The semiconductor device changes the potential of a first electrode of the first capacitance means and the potential of a first electrode of the second capacitance means from a first potential to a second potential thereby enlarging the difference between a potential input in a second electrode of the first capacitance means and a potential input in a second electrode of the second capacitance means and comparing the potential input in the second electrode of the first capacitance means and the potential input in the second electrode of the second capacitance means with each other.

Abstract: The digital broadcast receiving apparatus according to the present invention includes a tuning unit for outputting normal image data for performing a normal reproduction operation corresponding to a user selected channel, a memory unit for outputting background image data for performing a background reproduction operation when the normal reproduction operation cannot be performed, a data selector for receiving the normal image data and the background image data and outputting one of the normal image data and the background image data, and an MPEG video decode unit for decoding image data output by the data selector to generate an image signal. The tuning unit successively receives the respective channel selected in the background independently of the user selection, and stores the background image data corresponding to the respective channels in the memory unit.

Abstract: A semiconductor memory device capable of improving the operating speed while suppressing size increase is provided. This semiconductor device comprises a plurality of word lines and a plurality of bit lines arranged to intersect with each other, a single-port SRAM cell, connected to the bit lines and the word lines, having a single port for inputting/outputting data, a first row decoder and a second row decoder connected to the word lines for selecting a row address and a first column decoder and a second column decoder connected to the bit lines for selecting a column address, while each word line is divided into a plurality of local word lines.

Abstract: The digital broadcast receiving apparatus according to the present invention includes a tuning unit for outputting normal image data for performing a normal reproduction operation corresponding to a user selected channel, a memory unit for outputting background image data for performing a background reproduction operation when the normal reproduction operation cannot be performed, a data selector for receiving the normal image data and the background image data and outputting one of the normal image data and the background image data, and an MPEG video decode unit for decoding image data output by the data selector to generate an image signal. The tuning unit successively receives the respective channel selected in the background independently of the user selection, and stores the background image data corresponding to the respective channels in the memory unit.

Abstract: A printing section has a platen and a printhead which are oppositely located on both sides of a guide path for guiding the paper. A cutter section has a stationary blade and a movable blade located oppositely to either one of the platen and the printhead on both sides of the guide path. At the cutter section, the paper printed at the printing section is cut by engagement between the stationary blade and the movable blade. Either one of the stationary blade and the movable blade is held on a first unit located on one side of the guide path. On the other hand, either the other of the platen and the printhead and either the other of the stationary blade and the movable blade are held on a second unit which is located on the other side of the guide path. That is, the printing section and the cutter section are constructed by thus connecting the first unit to the second unit assembled as described above.

Abstract: A memory capable of reducing the memory cell size is provided. In this memory, a first gate electrode of a first selection transistor and a second gate electrode of a second selection transistor are provided integrally with a word line, and arranged to obliquely extend with respect to the longitudinal direction of a first impurity region on a region formed with memory cells and to intersect with the first impurity region on regions formed with the first selection transistor and the second selection transistor in plan view.

Abstract: A memory capable of reducing the memory cell size is provided. This memory comprises a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.

Abstract: A printer comprising a printing section that has a platen, a cutter section with a stationary blade and a movable blade and a printhead located oppositely on both sides of the guide path. A first unit is located on one side of the guide path arranged inside the casing which can be separated into a first casing member and a second casing member, holding either one of the stationary blade and the movable blade in the cutter section and a second unit located on the other side of the guide path that has either one of the other platen and the other printhead and either one of the other stationary blade and the other movable blade.

Abstract: A semiconductor memory device capable of improving the operating speed while suppressing size increase is provided. This semiconductor device comprises a plurality of word lines and a plurality of bit lines arranged to intersect with each other, a single-port SRAM cell, connected to the bit lines and the word lines, having a single port for inputting/outputting data, a first row decoder and a second row decoder connected to the word lines for selecting a row address and a first column decoder and a second column decoder connected to the bit lines for selecting a column address, while each word line is divided into a plurality of local word lines.