Abstract: A receiver for receiving signals in a plurality of transmission schemes, reducing the circuit size thereof successfully. The receiver for receiving a baseband signal and a modulated signal, includes a first PLL circuit configured to generate a first internal clock based on an external clock synchronized with the baseband signal; a demodulator configured to demodulate the modulated signal to output the demodulated signal; a selector configured to select one of the baseband signal or the demodulated signal; and a first CDR circuit configured to generate a recovered clock and recovered data from the signal selected by the selector, by using the first internal clock.

Abstract: In a synchronous reproduction signal processor, when a phase error between reproduction data and a clock is repeatedly detected such that a clock synchronized with a reproduction signal is generated based on the phase error, a filtering process unit (34) performs a filtering process which performs a weighed addition with respect to a phase error series prior to the current time from a phase error calculation unit (33) using, e.g., a FIR filter with a plurality of taps so as to generate a reference value under reduced influence of noise mixed in the phase error series by feedback correction. A cross detection unit (32) detects the timing with which the sampled reproduction data crosses the reference value generated by the filtering process unit (34). This allows effective use of the dynamic range of the feedbacked reference value without limiting it, and simultaneously achieves the enhancement of noise immunity.

Abstract: In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit.

Abstract: In a feedforward control type reproduced signal processor, a clock generator 1 changes a clock frequency, depending on a digital value set by a digital value generator 7. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculator 3 satisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator 1. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generator 1 gradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.

Abstract: A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz.

Abstract: In a wireless receiver, a “variance” of an intermediate output signal of a demodulation section is calculated by a variance calculation section, and the calculated variance is used as a signal quality indicator which indicates the degree of goodness of a receiving condition. For example, when the “variance” is small, a gain of a low-noise amplifier is reduced, or an operation clock frequency of a baseband oscillator is reduced, etc. Thus, when the receiving condition indicated by the indicator is good and sufficient performance is ensured, the performance can be slightly lowered to reduce power consumption. The “variance” is a compact indicator which can be calculated using a simple operation, and is used as a new signal quality indicator.

Abstract: A receiver for receiving signals in a plurality of transmission schemes, reducing the circuit size thereof successfully. The receiver for receiving a baseband signal and a modulated signal, includes a first PLL circuit configured to generate a first internal clock based on an external clock synchronized with the baseband signal; a demodulator configured to demodulate the modulated signal to output the demodulated signal; a selector configured to select one of the baseband signal or the demodulated signal; and a first CDR circuit configured to generate a recovered clock and recovered data from the signal selected by the selector, by using the first internal clock.

Abstract: A sheet processing apparatus of the invention has: a movement blocking unit for blocking a movement of a sheet which is moved to a side edge aligning unit by a moving unit, thereby allowing the moving unit to position adjustment slip move on the sheet so as to adjust a relative position with the sheet; and a block cancelling unit for allowing the movement blocking unit to cancel the block of the movement of the sheet when the moving unit slips and moves by a predetermined distance.

Abstract: In a digital PLL circuit outputting a clock signal with a frequency obtained by multiplying a frequency of a reference signal by a frequency command word (a frequency ratio), an RPA serially adds a frequency command word containing a fractional component. An output of the RPA is input to a minute phase error generator. The phase error generator generates a plurality of threshold values close to an actual amplitude value of the reference signal based on the fractional portion of the serially added value of the frequency command word, calculates the amplitude value of the reference signal and a phase error of the reference signal corresponding to the amplitude value based on the threshold values, and calculates a minute phase error between the reference signal and the output clock.

Abstract: Disclosed is a photodiode array comprising a semiconductor substrate; a plurality of photodiodes formed on the semiconductor substrate; and crystal fused regions losing crystallinity by fusing a semiconductor material of the photodiodes between the plurality of photodiodes.

Abstract: In a phase comparator used for a sync clock extraction circuit for extracting a clock synchronizing with reproduction data, a zero cross detection section 701, receiving the reproduction data, outputs a rising cross detection signal, a falling cross detection signal and three phase error candidates that are three consecutive samples. Rising and falling reference value hold sections 703 and 704 respectively output rising and falling reference values. When receiving the rising or falling cross detection signal, a phase error calculation section 702 outputs a sample the difference of which from the rising or falling reference value is minimum in absolute value, out of the three samples including a zero cross sample, as a phase error. The phase error is held in the rising or falling reference value hold section 703 or 704 as the rising or falling reference value for the next phase error calculation.

Abstract: A synchronization control circuit is provided with a first sampling means for sampling the envelope signal of the modulation signal at a first sampling timing, a second sampling means for sampling the envelope signal at a second sampling timing, a third sampling means for sampling the envelope signal at a third sampling timing, a phase error calculation means for calculating a phase error value indicating the amount of synchronization deviation between the modulation signal and the reference clock signal using the outputs of the first, second, and third sampling means, a delay control means for generating a delay control signal on the basis of the phase error value, and a delay generation means for generating the first, second, and third sampling timing by delaying the reference clock signal based on the delay control signal. Thereby, a synchronization control circuit that can reduce the circuit size required for obtaining the synchronization with relative to the Early/Late system can be provided.

Abstract: A low-molecular-weight water-soluble elastin having a molecular weight of about 10,000 to 30,000 and a high-molecular-weight water-soluble elastin having a molecular weight of about 30,000 to 300,000 are provided, 79% to 84% of the constituent amino acids of the elastin comprising proline, glycine, alanine, and valine, 2% to 3% comprising aspartic acid and glutamic acid, 0.7% to 1.3% comprising lysine, histidine, and arginine, and 0.2% to 0.4% comprising desmosine and isodesmosine. The low-molecular-weight water-soluble elastin that is obtained may be used in a functional food or a medicine. Such a high-purity water-soluble elastin may be produced by obtaining pure insoluble elastin by subjecting animal body tissue to a collagen removal treatment and then fragmenting the insoluble elastin by means of a solubilizing liquid. It may be produced simply, merely by adjusting the concentration of an alkaline solution and the reaction time without recovering insoluble elastin from the animal body tissue.

Abstract: A sheet processing apparatus nicely performs an aligning operation for a sheet conveyed onto a process tray with a simple configuration. A switching member performs an operation of switching an aligning member from a non-contact state to a contact state before the sheet reaches a contact position on the tray or performs an operation of, while the sheet on the tray is being conveyed toward a sheet edge regulating member by the aligning member, switching the aligning member from the contact state to the non-contact state, and further switching the aligning member from the non-contact state to the contact state. Thus, the sheet processing apparatus reduces an occurrence of a conveyance failure caused by collision of a leading edge of thick paper with a return roller and a return guide member, and maintains good conveyance performance by preventing sheet stick caused by a coating material coated on coat paper.

Abstract: A reactor includes a tubular coil and a core. The coil generates magnetic flux when a current is supplied thereto. The core is made of magnetic powder-containing resin, and is arranged to cover the coil. An entire surface of the coil is covered with an insulation coating. The insulation coating has corner portions that cover corner portions of the coil. The corner portions of the coil are formed between two opposing end surfaces (axial end surfaces) of the coil and an inner circumference surface of the coil, and between the two axial end surfaces of the coil and an outer circumference surface of the coil, when viewed in a cross section that is perpendicular to the direction the coil is wound. Each corner portion includes a curved surface portion formed with a circularly curved surface portion having a curvature radius of 0.2 mm or more. A minimum thickness of the corner portion is 0.2 mm or more. The elastic modulus of the core is 5 to 25 GPa.

Abstract: A piping joint that enables welding without back shielding and without oxidized scaling on the pipe's inner surface. A piping joint has an inner fitting portion formed around the circumference of an end of a first tubular material, and a first bevel is formed on the radial outside of the inner fitting portion around the circumference. An outer fitting portion, fitted to the radial outside of the inner fitting portion, is formed on the end of a second tubular material butt welded to the first tubular material, and a second bevel is formed around the circumference at the end of the outer fitting portion facing the first bevel. The cross-section of the face of the inner fitting portion located on the radial outside, and the cross-section of the face of the outer fitting portion located on the radial inside, are completely round with a constant circumferential curvature.

Abstract: In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section 2 calculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizer 6 by utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control section 4 controls the frequency dividing rate of the frequency synthesizer 6 in such a manner that the frequency ratio calculated by the frequency ratio calculation section 2 has a set value. Thus, as compared with a case in which the output clock of the frequency synthesizer 6 is a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.

Abstract: In a feedforward control type reproduced signal processor, a clock generator 1 changes a clock frequency, depending on a digital value set by a digital value generator 7. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculator 3 satisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator 1. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generator 1 gradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.

Abstract: A semiconductor photodetector 10 has a first semiconductor substrate 1 that is of a first conductive type and a low resistivity and has a (111) front surface, and a second semiconductor substrate 2 that is of the first conductive type and a high resistivity, has a (100) front surface, and is adhered onto first semiconductor substrate 1. A semiconductor region 3 of a second conductive type is formed on the front surface side of second semiconductor substrate 2. A region of a periphery of semiconductor region 3 is etched until first semiconductor substrate 1 is exposed. A first electrode 1e and a second electrode 2e are electrically connected to the exposed front surface of first semiconductor substrate 1 and to semiconductor region 3, respectively.

Abstract: In a synchronous reproduction signal processor, when a phase error between reproduction data and a clock is repeatedly detected such that a clock synchronized with a reproduction signal is generated based on the phase error, a filtering process unit (34) performs a filtering process which performs a weighed addition with respect to a phase error series prior to the current time from a phase error calculation unit (33) using, e.g., a FIR filter with a plurality of taps so as to generate a reference value under reduced influence of noise mixed in the phase error series by feedback correction. A cross detection unit (32) detects the timing with which the sampled reproduction data crosses the reference value generated by the filtering process unit (34). This allows effective use of the dynamic range of the feedbacked reference value without limiting it, and simultaneously achieves the enhancement of noise immunity.