Abstract: An object of the present invention is to provide a silver compound paste which can be easily applied without containing resin, and which produces a conductive film having a low electric resistivity by heating under conditions substantially equivalent to those in a conductive film containing a polymer type conductive paste. The present invention provides a silver compound paste containing silver oxide particles and a tertiary fatty acid silver salt.

Abstract: The present invention is made to improve the conventional analog processing that is easily affected by variations in semiconductor processing. This invention provides a wobble signal processing apparatus that can reduce the circuit scale and the power consumption as well as improve the quality of signal processing. The wobble signal processing apparatus of the present invention digitally processes a part that has conventionally been processed by an analog system, and further a PRML circuit is provided to implement error detection, whereby the circuit scale and the power consumption is reduced. This improves the detection of a signal that is inputted to the wobble signal processing apparatus.

Abstract: For the purpose of achieving reproduction of data recorded in an optical disc, or the like, with high accuracy and hence increasing the recording density, a digital filter is provided at a position between an A/D converter and an adaptive equalizing filter and between the A/D converter and a PLL circuit. Basically, an analog filter has only a low pass function. In a learning period prior to reproduction, a controller section sets various tap coefficients in the digital filter to determine a tap coefficient such that a jitter value detected in the PLL circuit is minimum. In a reproduction operation, the determined tap coefficient is set in the digital filter to perform optimum pre-equalization, and as a result, reproduction of data is performed with high accuracy.

Abstract: A D/A converter in an analog-digital mixed loop is realized with a reduced circuit area without sacrificing the resolution. A bit modulation section modulates an m-bit digital control signal, which is output from a digital section, into an n-bit (n<m) intermediate digital signal whose temporal average precision is substantially m bits. A D/A conversion section converts the intermediate digital signal into an intermediate analog signal having a range corresponding to m bits. Then, by the smoothing operation through an analog filter, the intermediate analog signal is output as an analog control signal that has an m-bit precision as that of the original signal. In this way, it is possible to reduce the bit width for the internal operation and thus to reduce the circuit area without sacrificing the resolution of a D/A converter.

Abstract: Disclosed are a back illuminated photodiode array, which is mass-producible and has an ultra-thin high-performance single-sided electrode structure, and a method of manufacturing the same. Both electrodes of a photodiode on a semiconductor substrate 1, which are anode and cathode, are collected on one plane of the substrate. The collection of the electrodes is achieved by electrically introducing one of them to the other plane via a hole H penetrating the semiconductor substrate 1. The semiconductor substrate 1 is thinned by polishing, and thus the time for forming the hole H is shortened. Moreover, during the manufacturing process, a supporting plate 3 is attached to the semiconductor substrate for reinforcing the thinned substrate. Thus, handling of a wafer during the process becomes easy and complies with mass production.

Abstract: A D/A converter in an analog-digital mixed loop is realized with a reduced circuit area without sacrificing the resolution. A bit modulation section modulates an m-bit digital control signal, which is output from a digital section, into an n-bit (n<m) intermediate digital signal whose temporal average precision is substantially m bits. A D/A conversion section converts the intermediate digital signal into an intermediate analog signal having a range corresponding to m bits. Then, by the smoothing operation through an analog filter, the intermediate analog signal is output as an analog control signal that has an m-bit precision as that of the original signal. In this way, it is possible to reduce the bit width for the internal operation and thus to reduce the circuit area without sacrificing the resolution of a D/A converter.

Abstract: In a state where a PLL circuit is not locked, a gain control signal according to the difference between a peak value of a reproduced signal and the upper or lower limit value of the dynamic range of an A/D converter is given to a variable gain amplifier. In a state where the PLL circuit is locked, a gain control signal according to the difference between the reproduced signal and a reference value that corresponds to a level to which the reproduced signal belongs is given to the variable gain amplifier for each sampling point of the A/D converter. The variable gain amplifier amplifies the reproduced signal with a gain according to the gain control signal.

Abstract: In a state where a PLL circuit is not locked, a gain control signal according to the difference between a peak value of a reproduced signal and the upper or lower limit value of the dynamic range of an A/D converter is given to a variable gain amplifier. In a state where the PLL circuit is locked, a gain control signal according to the difference between the reproduced signal and a reference value that corresponds to a level to which the reproduced signal belongs is given to the variable gain amplifier for each sampling point of the A/D converter. The variable gain amplifier amplifies the reproduced signal with a gain according to the gain control signal.

Abstract: An oscillating clock frequency of a VFO (variable frequency oscillator) is controlled, using the results of addition of an output from a constant multiplier and an output from an accumulator, which is a result of accumulation of outputs from another constant multiplier, based on a phase error signal by setting the output from an enable-provided latch to 0 during a frequency pull-in operation. A control signal generating portion outputs a pulse at the Hi level as a control signal when completion of frequency pull-in is detected. The latch stores the output from the constant multiplier at the time when the control signal is supplied. Thus, a phase pull-in operation is started in the state where a latch output representing a frequency correction component is obtained. During the phase pull-in operation, the VFO is controlled using the result of addition of an output from the multiplier, an output from the accumulator and an output from the latch.

Abstract: A travelling-wave tube amplifier comprises a travelling-wave tube, a plurality of collector electrodes, a plurality of collector leads and at least one magnetic core. The travelling-wave tube causes interaction between an electron beam and an input high frequency signal to amplify the high frequency signal, and outputs the amplified high frequency signal. The plurality of the collector electrodes capture the electron beam which was subjected to velocity modulation by the interaction. The plurality of the collector electrodes are electrically connected to a power source via the plurality of the collector leads. The at least one magnetic core comprises a through hole. Any two of the plurality of the collector leads go through the through hole in one of the magnetic cores. Currents flowing through the two collector leads through the through hole in the magnetic core generate magnetic fluxes in the magnetic core. The directions of the generated magnetic fluxes are reversed from each other.

Abstract: A feed-forward controlled phase difference detector for detecting a phase difference using the output of a comparator included in an analog-to-digital converter, for example, is combined with a known digital feedback controlled phase difference detector for recovering a clock signal. The feed-forward controlled phase difference detector has its loop gain controlled adaptively. By utilizing these two types of phase difference detectors, a clock recovery circuit for recovering a clock signal synchronized to the data read out from a storage medium, for example, can operate faster and more stably.

Abstract: An oscillating clock frequency of a VFO (variable frequency oscillator) is controlled, using the results of addition of an output from a constant multiplier and an output from an accumulator, which is a result of accumulation of outputs from another constant multiplier, based on a phase error signal by setting the output from an enable-provided latch to 0 during a frequency pull-in operation. A control signal generating portion outputs a pulse at the Hi level as a control signal when completion of frequency pull-in is detected. The latch stores the output from the constant multiplier at the time when the control signal is supplied. Thus, a phase pull-in operation is started in the state where a latch output representing a frequency correction component is obtained. During the phase pull-in operation, the VFO is controlled using the result of addition of an output from the multiplier, an output from the accumulator and an output from the latch.

Abstract: In an adaptive auto equalizer for automatically amending a signal distorted through propagation in a transmission line to the expected value, each multiplication unit includes a plurality of weight coefficient holding units for storing weight coefficients. The number of these weight coefficient holding units is the same as the clock number which is equal to a delay required for updating the weight coefficients. An adder calculates weight coefficients every clock. The storage location of the calculated weight coefficients is switched by a selector, and the weight coefficients calculated every clock are serially held in a corresponding one of the weight coefficient holding units. The other selectors serially select one of the plurality of weight coefficient holding units and the weight coefficients thus held are given to the multiplication units.

Abstract: An insoluble cross-linked polypentapeptide is totally synthesized by preparing two modified linear polypentapeptides patterned on the polypentapeptide from the pentapeptide (Val.sub.1 -Pro.sub.2 -Gly.sub.3 -Val.sub.4 -Gly.sub.5) one of the repeating peptide sequences contained in tropoelastin, the precursor protein of the core of the elastic fiber of the vascular wall, and by cross-linking the modified polypentapeptides. One of the intermediate polypentapeptides is modified by replacing a portion of at least one of the amino acid residues with the residue of an amino acid having more than one amino function and the other is modified by replacing a portion of at least one of the amino acid residues with the residue of an amino acid having more than one carboxyl function, to provide free amino groups on the one intermediate and free carboxyl groups on the other for interreaction in the presence of a suitable cross-linking agent.

Abstract: An insoluble cross-linked polypentapeptide is totally synthesized by preparing two modified linear polypentapeptides patterned on the polypentapeptide from the pentapeptide (Val.sub.1 -Pro.sub.2 -Gly.sub.3 -Val.sub.4 -Gly.sub.5) one of the repeating peptide sequences contained in tropoelastin, the precursor protein of the core of the elastic fiber of the vascular wall, and by cross-linking the modified polypentapeptides. One of the intermediate polypentapeptides is modified by replacing a portion of at least one of the amino acid residues with the residue of an amino acid having more than one amino function and the other is modified by replacing a portion of at least one of the amino acid residues with the residue of an amino acid having more than one carboxyl function, to provide free amino groups on the one intermediate and free carboxyl groups on the other for interreaction in the presence of a suitable cross-linking agent.