Abstract: A permanent wave treatment device has a heating means (3) for setting hair of a to-be-treated person in a heated environment, a rod (R) on which the hair is wound and that is formed so that air can flow through it, a suction means (4) for making the pressure inside the rod negative, and a connection means (7) for connecting the rod and the suction means.

Abstract: A sheet processing apparatus of the invention has: a movement blocking unit for blocking a movement of a sheet which is moved to a side edge aligning unit by a moving unit, thereby allowing the moving unit to position adjustment slip move on the sheet so as to adjust a relative position with the sheet; and a block cancelling unit for allowing the movement blocking unit to cancel the block of the movement of the sheet when the moving unit slips and moves by a predetermined distance.

Abstract: When generating a sampling clock of an A/D converter for digitizing a playback signal from an optical disc, an over sampling clock generated by a PLL is used. Further, zerocross position information and reference information of a playback digital signal that is obtained by A/D conversion using the over sampling clock are converted into those synchronized with the channel bit clock by an operation cycle conversion unit, and then supplied to a PRML signal processing unit and a level judgement binarization unit.

Abstract: In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section 2 calculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizer 6 by utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control section 4 controls the frequency dividing rate of the frequency synthesizer 6 in such a manner that the frequency ratio calculated by the frequency ratio calculation section 2 has a set value. Thus, as compared with a case in which the output clock of the frequency synthesizer 6 is a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.

Abstract: In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2.

Abstract: In a phase error detecting circuit used in a synchronous clock extracting circuit for extracting a clock which is synchronized with reproduced data, a cross reference value generator 72 inputs, as a rising cross reference value S5, rising phase error data S3 calculated in a phase error calculator 71 to a rising cross detector 70a and inputs, as a falling cross reference value S6, falling phase error data S4 similarly calculated to a falling cross detector 70b. Each of the cross detectors 70a and 70b calculates a difference value between the value of the reproduced data at a sampling point and the inputted cross reference value (cross offset value) S5 or S6 and outputs a rising or falling cross detection signal when one of two difference values at consecutive sampling points is negative and the other thereof is positive. Accordingly, a capture range is enlarged.

Abstract: In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2.

Abstract: A low-molecular-weight water-soluble elastin having a molecular weight of about 10,000 to 30,000 and a high-molecular-weight water-soluble elastin having a molecular weight of about 30,000 to 300,000 are provided, 79% to 84% of the constituent amino acids of the elastin comprising proline, glycine, alanine, and valine, 2% to 3% comprising aspartic acid and glutamic acid, 0.7% to 1.3% comprising lysine, histidine, and arginine, and 0.2% to 0.4% comprising desmosine and isodesmosine. The low-molecular-weight water-soluble elastin that is obtained may be used in a functional food or a medicine. Such a high-purity water-soluble elastin may be produced by obtaining pure insoluble elastin by subjecting animal body tissue to a collagen removal treatment and then fragmenting the insoluble elastin by means of a solubilizing liquid. It may be produced simply, merely by adjusting the concentration of an alkaline solution and the reaction time without recovering insoluble elastin from the animal body tissue.

Abstract: Disclosed is a photodiode array comprising a semiconductor substrate; a plurality of photodiodes formed on the semiconductor substrate; and crystal fused regions losing crystallinity by fusing a semiconductor material of the photodiodes between the plurality of photodiodes.

Abstract: The present invention is made to improve the conventional analog processing that is easily affected by variations in semiconductor processing. This invention provides a wobble signal processing apparatus that can reduce the circuit scale and the power consumption as well as improve the quality of signal processing. The wobble signal processing apparatus of the present invention digitally processes a part that has conventionally been processed by an analog system, and a PRML circuit is further provided to implement error detection, whereby the circuit scale and the power consumption is reduced. This improves the detection of a signal that is inputted to the wobble signal processing apparatus.

Abstract: The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.

Abstract: A filter coefficient adjusting circuit of the present invention comprises a coefficient adjusting circuit (2) that adjusts an equalization coefficient by weighting an initial value of the equalization coefficient on the left side from a center tap of a FIR filter (1) that equalizes a reproduce signal, by a factor of n, and weighting an initial value of the equalization coefficient on the right side by a factor of (2?n), and determines the factor n of the weighting so as to optimize an output of a jitter detector (5), for example, that detects jitter between the reproduced signal and a clock, as an equalization performance detecting means that detects an equalization performance of the reproduce signal.

Abstract: A semiconductor photodetector 10 has a first semiconductor substrate 1 that is of a first conductive type and a low resistivity and has a (111) front surface, and a second semiconductor substrate 2 that is of the first conductive type and a high resistivity, has a (100) front surface, and is adhered onto first semiconductor substrate 1. A semiconductor region 3 of a second conductive type is formed on the front surface side of second semiconductor substrate 2. A region of a periphery of semiconductor region 3 is etched until first semiconductor substrate 1 is exposed. A first electrode 1e and a second electrode 2e are electrically connected to the exposed front surface of first semiconductor substrate 1 and to semiconductor region 3, respectively.

Abstract: Disclosed is a photodiode array comprising a semiconductor substrate; a plurality of photodiodes formed on the semiconductor substrate; and crystal fused regions losing crystallinity by fusing a semiconductor material of the photodiodes between the plurality of photodiodes.

Abstract: The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.

Abstract: In a phase error detecting circuit used in a synchronous clock extracting circuit for extracting a clock which is synchronized with reproduced data, a cross reference value generator 72 inputs, as a rising cross reference value S5, rising phase error data S3 calculated in a phase error calculator 71 to a rising cross detector 70a and inputs, as a falling cross reference value S6, falling phase error data S4 similarly calculated to a falling cross detector 70b. Each of the cross detectors 70a and 70b calculates a difference value between the value of the reproduced data at a sampling point and the inputted cross reference value (cross offset value) S5 or S6 and outputs a rising or falling cross detection signal when one of two difference values at consecutive sampling points is negative and the other thereof is positive. Accordingly, a capture range is enlarged.

Abstract: An object of the present invention is to provide a silver compound paste which can be easily applied without containing resin, and which produces a conductive film having a low electric resistivity by heating under conditions substantially equivalent to those in a conductive film containing a polymer type conductive paste. The present invention provides a silver compound paste containing silver oxide particles and a tertiary fatty acid silver salt.

Abstract: Disclosed are a back illuminated photodiode array, which is mass-producible and has an ultra-thin high-performance single-sided electrode structure, and a method of manufacturing the same. Both electrodes of a photodiode on a semiconductor substrate 1, which are anode and cathode, are collected on one plane of the substrate. The collection of the electrodes is achieved by electrically introducing one of them to the other plane via a hole H penetrating the semiconductor substrate 1. The semiconductor substrate 1 is thinned by polishing, and thus the time for forming the hole H is shortened. Moreover, during the manufacturing process, a supporting plate 3 is attached to the semiconductor substrate for reinforcing the thinned substrate. Thus, handling of a wafer during the process becomes easy and complies with mass production.

Abstract: A feed-forward controlled phase difference detector for detecting a phase difference using the output of a comparator included in an analog-to-digital converter, for example, is combined with a known digital feedback controlled phase difference detector for recovering a clock signal. The feed-forward controlled phase difference detector has its loop gain controlled adaptively. By utilizing these two types of phase difference detectors, a clock recovery circuit for recovering a clock signal synchronized to the data read out from a storage medium, for example, can operate faster and more stably.

Abstract: When generating a sampling clock of an A/D converter for digitizing a playback signal from an optical disc, an over sampling clock generated by a PLL is used. Further, zerocross position information and reference information of a playback digital signal that is obtained by A/D conversion using the over sampling clock are converted into those synchronized with the channel bit clock by an operation cycle conversion unit, and then supplied to a PRML signal processing unit and a level judgement binarization unit.