Abstract: In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

Abstract: Systems or methods of the present disclosure may provide a dual bump design to support both high voltage input/output (HVIO) connections and medium speed input/output (MSIO) connections. The present disclosure includes an MSIO lane that couples to a first bump that couples to MSIO pins, a second bump that couples to an HVIO circuit, and a ball grid array (BGA) ball. The present disclosure also includes a multiplexer that selectively couples the MSIO pins to the BGA ball or the HVIO circuit to the BGA ball based on user input. As such, the MSIO lane may provide MSIO connections, HVIO connections, or both.

Abstract: Some embodiments include an apparatus having a supply node, a conductive pad, and an electrostatic discharge (ESD) protection circuitry. The ESD protection circuitry includes a transistor including levels of semiconductor materials separated from each other and located one over another over a substrate. Respective portions of the levels of semiconductor materials form part of a channel, a source terminal, and a drain terminal of the transistor. The transistor includes a conductive material separated from the channel by a dielectric material and surrounding at least part of the channel. At least a portion of the conductive material forms part of a gate terminal of the transistor. The gate terminal is coupled to the supply node. The source terminal is coupled to the supply node. And the drain terminal is coupled to the conductive pad.

Abstract: An electronic interconnection device includes a guard ring that has a conductive region having a rectangular shape and a via filled with conductive material that is coupled to the conductive region. The guard ring is configured to provide shielding that reduces cross-coupling between inductors that are external to the electronic interconnection device. The via may extend to an external surface of the electronic interconnection device.

Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

Abstract: Described herein are packages in which photonic chiplets are disposed in recesses defined on an underlying substrate. Positioning chiplets in this way allows short trace lengths between the electrical chips and the optical converters, V-groove fiber assemblies that can be attached along any direction of a photonic chiplet (north-south and/or west-east) and easy access to the electrical chips for power and signals. A package may include a substrate having a recess defined near an edge of the substrate, a photonic chiplet disposed in the recess, an electrical chiplet disposed at least in part on the photonic chiplet, and a fiber optically coupled to the photonic chiplet at the edge of the substrate. The electrical chiplet may be disposed in part on the photonic chiplet and in part on the top surface of the substrate.

Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

Abstract: Embodiments disclosed herein include power transformers for microelectronic devices. In an embodiment, a power transformer comprises a magnetic core that is a closed loop with an inner dimension and an outer dimension, and a primary winding around the magnetic core. In an embodiment, the primary winding has a first number of first turns connected in series around the magnetic core. In an embodiment, a secondary winding is around the magnetic core, and the secondary winding has a second number of second turns around the magnetic core. In an embodiment, individual ones of the second turns comprise a plurality of secondary segments connected in parallel.

Abstract: A framework and a method for ad-hoc batch testing of APIs are provided, where batches of API calls are dynamically generated directly through the framework according inputs identifying the required tests and the sources of the test data, rather than through execution of prewritten test scripts that explicitly write out the test API calls in preset sequences. When performing the validation for an API test, a test payload is generated for the test, an endpoint is called using the test payload to obtain the response used for validation, where generating the test payload includes determining an API reference corresponding to the test, obtaining relevant data from the test data according to a reference key in the test, generating input assignment operations for one or more input parameters in the API reference according to the relevant data, and generating an API call based on the API reference.

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

Abstract: Systems or methods of the present disclosure may provide a multi-chip package with two or more integrated circuit devices that each include hybrid bumps. The hybrid bumps may include bumps of different sizes to facilitate different types of communication. For example, the hybrid bumps may include a first bump with fine pitch for die-to-die communication and/or a second bump with a large pitch for off-package communication. The multi-chip package may include a bridge to facilitate signal transfer between the integrated circuit device with the hybrid bumps and other components within the multi-chip package. Additionally or alternatively, the multi-chip package may include an interconnect to facilitate signal transfer between two integrated circuit devices. The interconnect may include fine pitch bumps, which may be translated by an interposer to a pitch size of the bridge. As such, the interconnect may facilitate die-to-die communication and/or off-package communication.

Abstract: Systems or methods of the present disclosure may provide an integrated circuit device that implements one region definition, which may decrease design complexity, decrease software complexity, and increase ease of use. For example, the integrated circuit device may include programmable logic that implements one region definition. The region definition may include circuitry that may implement three-dimensional (3D) input/output circuitry, 2.5D input/output circuitry, circuitry for intra-die communication, circuitry for inter-package communication, or any combination thereof. By implementing one region definition on the integrated circuit device, time spent defining each programmable logic region may be reduced or eliminated, thereby reducing design complexity software complexity associated with the integrated circuit device.

Abstract: An electronic device includes a first layer and a thermal heatsink that comprises a conductive region in a second layer of the electronic device. The thermal heatsink further comprises a first via that extends through the first layer. The first via is filled with conductive material that is coupled to the conductive region. The conductive material in the first via is coupled to an external terminal of the electronic device. The electronic device can also include a second via filled with conductive material that is coupled to the conductive region.

Abstract: An electronic device includes conductive pads that are formed on a surface of the electronic device. Each of the conductive pads has an oval shape. The conductive pads are coupled to deliver at least one of a power supply voltage or a ground voltage between an external device and the electronic device.

Abstract: An integrated circuit package includes first and second integrated circuit dies stacked vertically and coupled together, a connection device coupled to the first integrated circuit die, and a power delivery device coupled to the connection device. The power delivery device includes an inductor. The inductor generates supply current. The inductor is coupled to provide the supply current from the inductor to the first integrated circuit die through the connection device.

Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

Abstract: Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.