Patents by Inventor Krishna Bharath
Krishna Bharath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968264Abstract: A framework and a method are provided for monitoring and managing software bots that collectively automate business processes. The method includes interfacing with the bots executing on a bot infrastructure. The method also includes obtaining the bot-specific performance data and the infrastructure-level performance data recorded by the bots and the bot infrastructure. The method further includes generating or modifying a bot dependency chain based on the bot-specific performance data and the infrastructure-level performance data. The bot dependency chain represents at least one of dependencies amongst the bots and dependencies amongst the related business processes. The method also includes generating an outcome for the business processes according to the bot dependency chain and the bot-specific performance data and the infrastructure-level performance data recorded by the bots and the bot infrastructure.Type: GrantFiled: April 5, 2022Date of Patent: April 23, 2024Assignee: CONCENTRIX CVG CUSTOMER MANAGEMENT GROUP INC.Inventors: Ramanathan Sathianarayanan, Krishna Bharath Kashyap
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Publication number: 20240120302Abstract: An electronic device includes first and second external conductive pads coupled to route a first signal and third and fourth external conductive pads. The third and the fourth external conductive pads are between the first and the second external conductive pads on a surface of the electronic device.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Applicant: Intel CorporationInventors: Krishna Bharath Kolluru, Atul Maheshwari, Mahesh Kumashikar, Md Altaf Hossain, Ankireddy Nalamalpu, Omkar Karhade
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Patent number: 11955426Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.Type: GrantFiled: June 13, 2022Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
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Publication number: 20240111703Abstract: An active interconnection device has a repeater circuit that includes a storage circuit. The storage circuit is coupled to store a configuration bit for configuring the repeater circuit to transmit a signal between a first integrated circuit die and a second integrated circuit die. The storage circuit is coupled to receive the configuration bit through a conductor during a configuration mode. A buffer circuit in the repeater circuit is configurable to transmit the signal through the conductor during a transmission mode in response to the configuration bit.Type: ApplicationFiled: December 12, 2023Publication date: April 4, 2024Applicant: Altera CorporationInventors: Mahesh Kumashikar, Atul Maheshwari, Md Altaf Hossain, Ankireddy Nalamalpu, Krishna Bharath Kolluru
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Techniques For Shifting Signal Transmission To Compensate For Defects In Pads In Integrated Circuits
Publication number: 20240113014Abstract: An integrated circuit includes first external conductive pads, second external conductive pads, and third external conductive pads. The second external conductive pads are between the first external conductive pads and the third external conductive pads. Repair group circuitry is configurable to shift signal transmission away from one of the first external conductive pads to one of the third external conductive pads if the one of the first external conductive pads has a defect.Type: ApplicationFiled: December 13, 2023Publication date: April 4, 2024Applicant: Altera CorporationInventors: Krishna Bharath Kolluru, Atul Maheshwari, Mahesh Kumashikar, Md Altaf Hossain, Ankireddy Nalamalpu, Jeffrey Chromczak -
Patent number: 11922230Abstract: In some embodiments, an API specification document is processed to extract metadata representing API elements. Dependencies are mapped between the API elements using orders and ranks to create a metamodel that includes a map of metadata attributes and links that represent functional and operational aspects of program elements accessible via the API. The metamodel is stored for use in generating support infrastructure artifacts. In some embodiments, database entities are compared to a metamodel to generate matches. Each match indicates a confidence score and a relationship between a database entity and a metadata attribute. A selection of a metadata attribute is received for inclusion in the new API, and a selection of a database entity to be associated with the metadata attribute for the new API is received. The computing system updates the confidence score for the match that indicates the relationship between the database entity and the metadata attribute.Type: GrantFiled: April 6, 2023Date of Patent: March 5, 2024Assignee: CONEKTTO, INC.Inventors: Amol Dewhare, Ramanathan Sathianarayanan, Krishna Bharath Kashyap
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Patent number: 11916006Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.Type: GrantFiled: August 25, 2022Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Krishna Bharath, Shawna M. Liff, Johanna M. Swan
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Patent number: 11881457Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.Type: GrantFiled: March 4, 2021Date of Patent: January 23, 2024Assignee: Tahoe Research, Ltd.Inventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon
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Publication number: 20230418732Abstract: A framework and a method for ad-hoc batch testing of APIs are provided, where batches of API calls are dynamically generated directly through the framework according inputs identifying the required tests and the sources of the test data, rather than through execution of prewritten test scripts that explicitly write out the test API calls in preset sequences. When performing the validation for an API test, a test payload is generated for the test, an endpoint is called using the test payload to obtain the response used for validation, where generating the test payload includes determining an API reference corresponding to the test, obtaining relevant data from the test data according to a reference key in the test, generating input assignment operations for one or more input parameters in the API reference according to the relevant data, and generating an API call based on the API reference.Type: ApplicationFiled: May 22, 2023Publication date: December 28, 2023Inventors: Ramanathan Sathianarayanan, Krishna Bharath Kashyap
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Publication number: 20230397325Abstract: Technology is disclosed for a computing system with a printed circuit board having a top and bottom; an integrated circuit component coupled to the top of the board; a passive heat exchanger coupled to the top of the board and spaced from the integrated circuit component; at least one electronic component coupled to the printed circuit board below the top of the printed circuit board; and at least one heat pipe having an evaporator end adjacent the electronic component and extending away from the evaporator end along the bottom of the board to a condenser end above the top of the board, the condenser end being thermally coupled to the passive heat exchanger on the top of the board; wherein heat from electronic component is moved away from the electronic component and the integrated circuit component to the passive heat exchanger.Type: ApplicationFiled: June 3, 2022Publication date: December 7, 2023Inventors: Unnikrishnan VADAKKANMARU VEEDU, Silvia Anali SOTO DE LA TORRE, Alexander LYAKHOV, Krishna BHARATH, Fenghua SHEN, Madhavi TADEPALLI
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Patent number: 11791528Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.Type: GrantFiled: April 6, 2022Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
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Patent number: 11735535Abstract: Embodiments include an inductor, a method to form the inductor, and a semiconductor package. An inductor includes a plurality of plated-through-hole (PTH) vias in a substrate layer, and a plurality of magnetic interconnects with a plurality of openings in the substrate layer. The openings of the magnetic interconnects surround the PTH vias. The inductor also includes an insulating layer in the substrate layer, a first conductive layer over the PTH vias, magnetic interconnects, and insulating layer, and a second conductive layer below the PTH vias, magnetic interconnects, and insulating layer. The insulating layer surrounds the PTH vias and magnetic interconnects. The magnetic interconnects may have a thickness substantially equal to a thickness of the PTH vias. The magnetic interconnects may be shaped as hollow cylindrical magnetic cores with magnetic materials. The magnetic materials may include ferroelectric, conductive, or epoxy materials. The hollow cylindrical magnetic cores may be ferroelectric cores.Type: GrantFiled: October 8, 2019Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Kaladhar Radhakrishnan, Krishna Bharath, Clive Hendricks
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Publication number: 20230244552Abstract: In some embodiments, an API specification document is processed to extract metadata representing API elements. Dependencies are mapped between the API elements using orders and ranks to create a metamodel that includes a map of metadata attributes and links that represent functional and operational aspects of program elements accessible via the API. The metamodel is stored for use in generating support infrastructure artifacts. In some embodiments, database entities are compared to a metamodel to generate matches. Each match indicates a confidence score and a relationship between a database entity and a metadata attribute. A selection of a metadata attribute is received for inclusion in the new API, and a selection of a database entity to be associated with the metadata attribute for the new API is received. The computing system updates the confidence score for the match that indicates the relationship between the database entity and the metadata attribute.Type: ApplicationFiled: April 6, 2023Publication date: August 3, 2023Applicant: Conektto, Inc.Inventors: Amol Dewhare, Ramanathan Sathianarayanan, Krishna Bharath Kashyap
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Patent number: 11688729Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.Type: GrantFiled: July 9, 2018Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Adel Elsherbini, Krishna Bharath, Mathew Manusharow
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Publication number: 20230187407Abstract: A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.Type: ApplicationFiled: December 10, 2021Publication date: June 15, 2023Applicant: Intel CorporationInventors: Carleton L. Molnar, Adel A. Elsherbini, Tanay Karnik, Shawna M. Liff, Robert J. Munoz, Julien Sebot, Johanna M. Swan, Nevine Nassif, Gerald S. Pasdast, Krishna Bharath, Neelam Chandwani, Dmitri E. Nikonov
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Patent number: 11676950Abstract: An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.Type: GrantFiled: September 28, 2017Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Krishna Bharath, Sriram Srinivasan, Amruthavalli Alur, Kaladhar Radhakrishnan, Huong Do, William Lambert
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Patent number: 11675691Abstract: A framework and a method for ad-hoc batch testing of APIs are provided, where batches of API calls are dynamically generated directly through the framework according inputs identifying the required tests and the sources of the test data, rather than through execution of prewritten test scripts that explicitly write out the test API calls in preset sequences. When performing the validation for an API test, a test payload is generated for the test, an endpoint is called using the test payload to obtain the response used for validation, where generating the test payload includes determining an API reference corresponding to the test, obtaining relevant data from the test data according to a reference key in the test, generating input assignment operations for one or more input parameters in the API reference according to the relevant data, and generating an API call based on the API reference.Type: GrantFiled: July 5, 2022Date of Patent: June 13, 2023Assignee: PROKARMA, INC.Inventors: Ramanathan Sathianarayanan, Krishna Bharath Kashyap
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Publication number: 20230095063Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Beomseok Choi, William J. Lambert, Krishna Bharath, Kaladhar Radhakrishnan, Adel Elsherbini, Henning Braunisch, Stephen Morein, Aleksandar Aleksov, Feras Eid
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Publication number: 20230095654Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Adel Elsherbini, Feras Eid, Stephen Morein, Krishna Bharath, Henning Braunisch, Beomseok Choi, Brandon M. Rawlings, Thomas L. Sounart, Johanna Swan, Yoshihiro Tomita, Aleksandar Aleksov
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Publication number: 20230096368Abstract: An inductor structure, a package substrate, an integrated circuit device, an integrated circuit device assembly and a method of fabricating the inductor structure. The inductor structure includes: an electrically conductive body; and a magnetic structure including a non-electrically-conductive magnetic material, wherein: one of the magnetic structure or the electrically conductive body wraps around another one of the magnetic structure or the electrically conductive body to form the inductor structure therewith; and at least one of the electrically conductive body or the magnetic structure has a granular microstructure including randomly distributed particles presenting substantially non-linear particle-to-particle boundaries with one another.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Aleksandar Aleksov, Adel Elsherbini, Johanna Swan, Feras Eid, Thomas L. Sounart, Henning Braunisch, Beomseok Choi, Krishna Bharath, Kaladhar Radhakrishnan, William J. Lambert