Patents by Inventor Krishna Bharath

Krishna Bharath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10651525
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • Publication number: 20200105653
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Krishna Bharath, Shawna M. Liff, Johanna M. Swan
  • Publication number: 20200098621
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a first surface and an opposing second surface, wherein the first die is in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor may include a first conductive pillar at least partially surrounded by a magnetic material, and a second conductive pillar coupled to the first conductive pillar; and a second die having a first surface and an opposing second surface, wherein the second die is in a second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic core inductor.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Krishna Bharath, Adel A. Elsherbini, Shawna M. Liff, Kaladhar Radhakrishnan, Zhiguo Qian, Johanna M. Swan
  • Publication number: 20200098676
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die, having an active surface and an opposing backside surface, including a plurality of through silicon vias (TSVs); and an inductor including a first conductive pillar with a first end and an opposing second end, wherein the first end of the first conductive pillar is coupled to the backside surface of a first individual TSV; a second conductive pillar with a first end and an opposing second end, wherein the first end of the second conductive pillar is coupled to the backside surface of a second individual TSV, wherein the second end of the second conductive pillar is coupled to the second end of the first conductive pillar, and wherein the first and the second conductive pillars are at least partially surrounded in a magnetic material.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Bharath, Shawna M. Liff, Johanna M. Swan
  • Publication number: 20200091053
    Abstract: Disclosed herein are integrated circuit (IC) package supports having inductors with magnetic material therein. For example, in some embodiments, an IC package support may include an inductor including a solenoid, a first portion of a magnetic material in an interior of the solenoid, and a second portion of magnetic material outside the interior of the solenoid.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 19, 2020
    Applicant: Intel Corporation
    Inventors: Sameer Paital, Srinivas V. Pietambaram, Yonggang Li, Kristof Kuwawi Darmawikarta, Gang Duan, Krishna Bharath, Michael James Hill
  • Publication number: 20200066634
    Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
  • Publication number: 20200066830
    Abstract: A microelectronics package comprises a substrate comprising at least two conductive layers that are separated by a first dielectric. At least one island comprising a magnetic material is embedded within the dielectric between the two conductive layers. An inductor structure extends within a via in the at least one island. The via extends between the two conductive layers. The inductor structure comprises a conductive wall along a sidewall of the via, and wherein the conductive wall surrounds a second dielectric and is electrically coupled to the two conductive layers.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: Krishna Bharath, Wei-Lun Jen, Huong Do, Amruthavalli Alur
  • Publication number: 20200066627
    Abstract: A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 27, 2020
    Applicant: INTEL CORPORATION
    Inventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
  • Publication number: 20200013770
    Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: July 9, 2018
    Publication date: January 9, 2020
    Inventors: Adel Elsherbini, Krishna Bharath, Mathew Manusharow
  • Publication number: 20200004282
    Abstract: An apparatus is provided, where the apparatus includes a first domain including first one or more circuitries, and a second domain including second one or more circuitries. The apparatus may further include a first voltage regulator (VR) to supply power to the first domain from a power bus, a second VR to supply power to the second domain from the power bus, and a third VR coupled between the first and second domains. The third VR may at least one of: transmit power to at least one of the first or second domains, or receive power from at least one of the first or second domains.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: Beomseok Choi, Siddharth Kulasekaran, Krishna Bharath
  • Publication number: 20200006239
    Abstract: Embodiments herein relate to integrating FIVR switching circuitry into a substrate that has a first side and a second side opposite the first side, where the first side of the substrate to electrically couple with a die and to provide voltage to the die and the second side of the substrate is to couple with an input voltage source. In embodiments, the FIVR switching circuitry may be printed onto the substrate using OFET, CNT, or other transistor technology, or may be included in a separate die that is incorporated within the substrate.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Chong ZHANG, Krishna BHARATH
  • Publication number: 20200005989
    Abstract: A microelectronics package comprising a package core and an inductor over the package core. The inductor comprises a dielectric over the package core. The dielectric comprises a curved surface opposite the package core. At least one conductive trace is adjacent to the package core. The at least one conductive trace is at least partially embedded within the dielectric and extends over the package core. A magnetic core cladding is over the dielectric layer and at least partially surrounding the conductive trace.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Krishna Bharath, Adel Elsherbini
  • Publication number: 20200006305
    Abstract: A semiconductor package includes a first die and a second die. The first die includes a first plurality of compound semiconductor transistors, and where the first die includes a first section of a Power Management Circuitry (PMC). The second die includes a second plurality of transistors that are arranged as a plurality of CMOS (Complementary metal-oxide-semiconductor) circuitries, and where the second die includes a second section of the PMC. The PMC includes a power converter that includes: a plurality of power switches, a plurality of driver circuitries to correspondingly control the plurality of power switches, and a controller to control the driver circuitries. The first section of the PMC in the first die includes the plurality of power switches, and the second section of the PMC in the second die includes at least a part of the controller.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: William J. Lambert, Krishna Bharath, Beomseok Choi, Robert Sankman
  • Patent number: 10503227
    Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Krishna Bharath, Srikrishnan Venkataraman, William J. Lambert, Michael J. Hill, Alexander Slepoy, Dong Zhong, Kaladhar Radhakrishnan, Hector A. Aguirre Diaz, Jonathan P. Douglas
  • Publication number: 20190355636
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Inventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao
  • Patent number: 10410939
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao
  • Publication number: 20190259705
    Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.
    Type: Application
    Filed: September 30, 2016
    Publication date: August 22, 2019
    Inventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon
  • Patent number: 10186465
    Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Adel A. Elsherbini, Henning Braunisch, Yidnekachew S. Mekonnen, Krishna Bharath, Mathew J. Manusharow, Aleksandar Aleksov, Nathan Fritz
  • Publication number: 20180331003
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Application
    Filed: December 16, 2015
    Publication date: November 15, 2018
    Inventors: Krishna BHARATH, Mathew J. MANUSHAROW, Adel A. ELSHERBINI, Mihir K. ROY, Aleksandar ALEKSOV, Yidnekachew S. MEKONNEN, Javier SOTO GONZALEZ, Feras EID, Suddhasattwa NAD, Meizi JIAO
  • Publication number: 20180315690
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
    Type: Application
    Filed: December 21, 2015
    Publication date: November 1, 2018
    Inventors: Adel A. ELSHERBINI, Mathew J. MANUSHAROW, Krishna BHARATH, William J. LAMBERT, Robert L. SANKMAN, Aleksandar ALEKSOV, Brandon M. RAWLINGS, Feras EID, Javier SOTO GONZALEZ, Meizi JIAO, Suddhasattwa NAD, Telesphor KAMGAING