Patents by Inventor Krishna Bharath

Krishna Bharath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11404364
    Abstract: A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
  • Publication number: 20220232080
    Abstract: A framework and a method are provided for monitoring and managing software bots that collectively automate business processes. The method includes interfacing with the bots executing on a bot infrastructure. The method also includes obtaining the bot-specific performance data and the infrastructure-level performance data recorded by the bots and the bot infrastructure. The method further includes generating or modifying a bot dependency chain based on the bot-specific performance data and the infrastructure-level performance data. The bot dependency chain represents at least one of dependencies amongst the bots and dependencies amongst the related business processes. The method also includes generating an outcome for the business processes according to the bot dependency chain and the bot-specific performance data and the infrastructure-level performance data recorded by the bots and the bot infrastructure.
    Type: Application
    Filed: April 5, 2022
    Publication date: July 21, 2022
    Inventors: Ramanathan Sathianarayanan, Krishna Bharath Kashyap
  • Publication number: 20220231394
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Application
    Filed: April 6, 2022
    Publication date: July 21, 2022
    Inventors: Adel A. ELSHERBINI, Mathew MANUSHAROW, Krishna BHARATH, Zhichao ZHANG, Yidnekachew S. MEKONNEN, Aleksandar ALEKSOV, Henning BRAUNISCH, Feras EID, Javier SOTO
  • Patent number: 11393751
    Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
  • Patent number: 11380652
    Abstract: An apparatus is provided which comprises: a first set of one or more contacts on a first die surface, the first set of one or more contacts to couple with contacts of an integrated circuit die, one or more multi-level voltage clamps coupled with the first set of one or more contacts, the one or more multi-level voltage clamps switchable between two or more voltages, one or more integrated voltage regulators coupled with the one or more multi-level voltage clamps, the one or more integrated voltage regulators to provide an output voltage, one or more through silicon vias (TSVs) coupled with the one or more integrated voltage regulators, and a second set of one or more contacts on a second die surface, opposite the first die surface, the second set of one or more contacts coupled with the one or more TSVs, and the second set of one or more contacts to couple with contacts of a package substrate. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Beomseok Choi, Kaladhar Radhakrishnan, William Lambert, Michael Hill, Krishna Bharath
  • Patent number: 11379348
    Abstract: A framework and a method for ad-hoc batch testing of APIs are provided, where batches of API calls are dynamically generated directly through the framework according inputs identifying the required tests and the sources of the test data, rather than through execution of prewritten test scripts that explicitly write out the test API calls in preset sequences. When performing the validation for an API test, a test payload is generated for the test, an endpoint is called using the test payload to obtain the response used for validation, where generating the test payload includes determining an API reference corresponding to the test, obtaining relevant data from the test data according to a reference key in the test, generating input assignment operations for one or more input parameters in the API reference according to the relevant data, and generating an API call based on the API reference.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: July 5, 2022
    Assignee: ProKarma Inc.
    Inventors: Ramanathan Sathianarayanan, Krishna Bharath Kashyap
  • Patent number: 11353900
    Abstract: An apparatus is provided, where the apparatus includes a first domain including first one or more circuitries, and a second domain including second one or more circuitries. The apparatus may further include a first voltage regulator (VR) to supply power to the first domain from a power bus, a second VR to supply power to the second domain from the power bus, and a third VR coupled between the first and second domains. The third VR may at least one of: transmit power to at least one of the first or second domains, or receive power from at least one of the first or second domains.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventors: Beomseok Choi, Siddharth Kulasekaran, Krishna Bharath
  • Patent number: 11329358
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • Patent number: 11297144
    Abstract: A framework and a method are provided for monitoring and managing software bots that collectively automate business processes. The method includes interfacing with the bots executing on a bot infrastructure. The method also includes obtaining the bot-specific performance data and the infrastructure-level performance data recorded by the bots and the bot infrastructure. The method further includes generating or modifying a bot dependency chain based on the bot-specific performance data and the infrastructure-level performance data. The bot dependency chain represents at least one of dependencies amongst the bots and dependencies amongst the related business processes. The method also includes generating an outcome for the business processes according to the bot dependency chain and the bot-specific performance data and the infrastructure-level performance data recorded by the bots and the bot infrastructure.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 5, 2022
    Assignee: ProKarma Inc.
    Inventors: Ramanathan Sathianarayanan, Krishna Bharath Kashyap
  • Publication number: 20220102055
    Abstract: Embodiments disclosed herein include electronic packages with embedded inductors and methods of forming such electronic packages. In an embodiment, the electronic package comprises a package core, and a plated through hole (PTH) through a thickness of the package core. In an embodiment, the electronic package further and a magnetic shell around a perimeter of the PTH, where a height of the magnetic shell is less than the thickness of the package core. In an embodiment, the magnetic shell comprises a substantially vertical sidewall and a bottom surface that is tapered.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Brandon C. MARIN, Krishna BHARATH, Haifa HARIRI, Tarek A. IBRAHIM
  • Publication number: 20220102261
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 31, 2022
    Inventors: Adel A. ELSHERBINI, Mathew J. MANUSHAROW, Krishna BHARATH, William J. LAMBERT, Robert L. SANKMAN, Aleksandar ALEKSOV, Brandon M. RAWLINGS, Feras EID, Javier SOTO GONZALEZ, Meizi JIAO, Suddhasattwa NAD, Telesphor KAMGAING
  • Publication number: 20220093492
    Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Bharath, Han Wui Then, Kimin Jun, Aleksandar Aleksov, Mohammad Enamul Kabir, Shawna M. Liff, Johanna M. Swan, Feras Eid
  • Publication number: 20220093546
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Bharath, Kevin P. O'Brien, Kimin Jun, Han Wui Then, Mohammad Enamul Kabir, Gerald S. Pasdast, Feras Eid, Aleksandar Aleksov, Johanna M. Swan, Shawna M. Liff
  • Publication number: 20220093565
    Abstract: Embodiments disclosed herein include voltage regulators VR integrated into an electronic device. In an embodiment, an electronic device comprises a package substrate, a first die electrically coupled to the package substrate, and a second die with a first surface facing the first die and second surface facing the package substrate that is electrically coupled to the package substrate and the first die. In an embodiment, the second die is between the package substrate and the first die. In an embodiment, the second die comprises voltage regulation (VR) circuitry. In an embodiment current is received by the second die through only the first surface and the current only exits the second die through the second surface.
    Type: Application
    Filed: September 24, 2020
    Publication date: March 24, 2022
    Inventors: Kaladhar RADHAKRISHNAN, Krishna BHARATH
  • Publication number: 20220093314
    Abstract: Embodiments disclosed herein include power transformers for microelectronic devices. In an embodiment, a power transformer comprises a magnetic core that is a closed loop with an inner dimension and an outer dimension, and a primary winding around the magnetic core. In an embodiment, the primary winding has a first number of first turns connected in series around the magnetic core. In an embodiment, a secondary winding is around the magnetic core, and the secondary winding has a second number of second turns around the magnetic core. In an embodiment, individual ones of the second turns comprise a plurality of secondary segments connected in parallel.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Inventors: Anuj MODI, Huong DO, William J. LAMBERT, Krishna BHARATH, Harish KRISHNAMURTHY
  • Publication number: 20220094263
    Abstract: Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Inventors: Krishna BHARATH, Christopher SCHAEF, William J. LAMBERT, Kaladhar RADHAKRISHNAN
  • Publication number: 20220093536
    Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Inventors: Krishna BHARATH, William J. LAMBERT, Haifa HARIRI, Siddharth KULASEKARAN, Mathew MANUSHAROW, Anne AUGUSTINE
  • Patent number: 11227825
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew J. Manusharow, Krishna Bharath, William J. Lambert, Robert L. Sankman, Aleksandar Aleksov, Brandon M. Rawlings, Feras Eid, Javier Soto Gonzalez, Meizi Jiao, Suddhasattwa Nad, Telesphor Kamgaing
  • Patent number: 11211866
    Abstract: An adjustable inductance system includes a plurality of inductor modules coupled to a corresponding plurality of loads and a pool of at least one floating inductor module that may be coupled in parallel with any one of the plurality of inductor modules. A control circuit monitors the current drawn through the inductor module by the load. If current draw exceeds a threshold, the control circuit couples a floating inductor module to the load. Using the current drawn by the load, the control circuit determines an appropriate inductance value and determines an appropriate inductor configuration for the inductor module, the floating inductor module, or both the inductor module and the floating inductor module to achieve the determined inductance value. The control circuit causes switching elements to transition to a state or position to achieve the inductor configuration.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: William J. Lambert, Kaladhar Radhakrishnan, Beomseok Choi, Krishna Bharath, Michael J. Hill
  • Publication number: 20210398895
    Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 23, 2021
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Feras Eid, Georgios Dogiamis, Beomseok Choi, Henning Braunisch, William Lambert, Krishna Bharath, Johanna Swan