Patents by Inventor Krishna Bharath

Krishna Bharath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240312905
    Abstract: An integrated circuit package includes first and second integrated circuit dies stacked vertically and coupled together, a connection device coupled to the first integrated circuit die, and a power delivery device coupled to the connection device. The power delivery device includes an inductor. The inductor generates supply current. The inductor is coupled to provide the supply current from the inductor to the first integrated circuit die through the connection device.
    Type: Application
    Filed: May 29, 2024
    Publication date: September 19, 2024
    Applicant: Altera Corporation
    Inventors: Md Altaf Hossain, Atul Maheshwari, Mahesh Kumashikar, Ankireddy Nalamalpu, Krishna Bharath Kolluru
  • Patent number: 12087682
    Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: September 10, 2024
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Feras Eid, Georgios Dogiamis, Beomseok Choi, Henning Braunisch, William Lambert, Krishna Bharath, Johanna Swan
  • Patent number: 12068684
    Abstract: Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: August 20, 2024
    Assignee: Intel Corporation
    Inventors: Krishna Bharath, Christopher Schaef, William J. Lambert, Kaladhar Radhakrishnan
  • Patent number: 12062631
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 13, 2024
    Assignee: Intel Corporation
    Inventors: Adel A Elsherbini, Krishna Bharath, Kevin P. O'Brien, Kimin Jun, Han Wui Then, Mohammad Enamul Kabir, Gerald S. Pasdast, Feras Eid, Aleksandar Aleksov, Johanna M. Swan, Shawna M. Liff
  • Patent number: 12002745
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: June 4, 2024
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew J. Manusharow, Krishna Bharath, William J. Lambert, Robert L. Sankman, Aleksandar Aleksov, Brandon M. Rawlings, Feras Eid, Javier Soto Gonzalez, Meizi Jiao, Suddhasattwa Nad, Telesphor Kamgaing
  • Patent number: 11968264
    Abstract: A framework and a method are provided for monitoring and managing software bots that collectively automate business processes. The method includes interfacing with the bots executing on a bot infrastructure. The method also includes obtaining the bot-specific performance data and the infrastructure-level performance data recorded by the bots and the bot infrastructure. The method further includes generating or modifying a bot dependency chain based on the bot-specific performance data and the infrastructure-level performance data. The bot dependency chain represents at least one of dependencies amongst the bots and dependencies amongst the related business processes. The method also includes generating an outcome for the business processes according to the bot dependency chain and the bot-specific performance data and the infrastructure-level performance data recorded by the bots and the bot infrastructure.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: April 23, 2024
    Assignee: CONCENTRIX CVG CUSTOMER MANAGEMENT GROUP INC.
    Inventors: Ramanathan Sathianarayanan, Krishna Bharath Kashyap
  • Publication number: 20240120302
    Abstract: An electronic device includes first and second external conductive pads coupled to route a first signal and third and fourth external conductive pads. The third and the fourth external conductive pads are between the first and the second external conductive pads on a surface of the electronic device.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Applicant: Intel Corporation
    Inventors: Krishna Bharath Kolluru, Atul Maheshwari, Mahesh Kumashikar, Md Altaf Hossain, Ankireddy Nalamalpu, Omkar Karhade
  • Patent number: 11955426
    Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
  • Publication number: 20240113014
    Abstract: An integrated circuit includes first external conductive pads, second external conductive pads, and third external conductive pads. The second external conductive pads are between the first external conductive pads and the third external conductive pads. Repair group circuitry is configurable to shift signal transmission away from one of the first external conductive pads to one of the third external conductive pads if the one of the first external conductive pads has a defect.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 4, 2024
    Applicant: Altera Corporation
    Inventors: Krishna Bharath Kolluru, Atul Maheshwari, Mahesh Kumashikar, Md Altaf Hossain, Ankireddy Nalamalpu, Jeffrey Chromczak
  • Publication number: 20240111703
    Abstract: An active interconnection device has a repeater circuit that includes a storage circuit. The storage circuit is coupled to store a configuration bit for configuring the repeater circuit to transmit a signal between a first integrated circuit die and a second integrated circuit die. The storage circuit is coupled to receive the configuration bit through a conductor during a configuration mode. A buffer circuit in the repeater circuit is configurable to transmit the signal through the conductor during a transmission mode in response to the configuration bit.
    Type: Application
    Filed: December 12, 2023
    Publication date: April 4, 2024
    Applicant: Altera Corporation
    Inventors: Mahesh Kumashikar, Atul Maheshwari, Md Altaf Hossain, Ankireddy Nalamalpu, Krishna Bharath Kolluru
  • Patent number: 11922230
    Abstract: In some embodiments, an API specification document is processed to extract metadata representing API elements. Dependencies are mapped between the API elements using orders and ranks to create a metamodel that includes a map of metadata attributes and links that represent functional and operational aspects of program elements accessible via the API. The metamodel is stored for use in generating support infrastructure artifacts. In some embodiments, database entities are compared to a metamodel to generate matches. Each match indicates a confidence score and a relationship between a database entity and a metadata attribute. A selection of a metadata attribute is received for inclusion in the new API, and a selection of a database entity to be associated with the metadata attribute for the new API is received. The computing system updates the confidence score for the match that indicates the relationship between the database entity and the metadata attribute.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: March 5, 2024
    Assignee: CONEKTTO, INC.
    Inventors: Amol Dewhare, Ramanathan Sathianarayanan, Krishna Bharath Kashyap
  • Patent number: 11916006
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Krishna Bharath, Shawna M. Liff, Johanna M. Swan
  • Patent number: 11881457
    Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: January 23, 2024
    Assignee: Tahoe Research, Ltd.
    Inventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon
  • Publication number: 20230418732
    Abstract: A framework and a method for ad-hoc batch testing of APIs are provided, where batches of API calls are dynamically generated directly through the framework according inputs identifying the required tests and the sources of the test data, rather than through execution of prewritten test scripts that explicitly write out the test API calls in preset sequences. When performing the validation for an API test, a test payload is generated for the test, an endpoint is called using the test payload to obtain the response used for validation, where generating the test payload includes determining an API reference corresponding to the test, obtaining relevant data from the test data according to a reference key in the test, generating input assignment operations for one or more input parameters in the API reference according to the relevant data, and generating an API call based on the API reference.
    Type: Application
    Filed: May 22, 2023
    Publication date: December 28, 2023
    Inventors: Ramanathan Sathianarayanan, Krishna Bharath Kashyap
  • Publication number: 20230397325
    Abstract: Technology is disclosed for a computing system with a printed circuit board having a top and bottom; an integrated circuit component coupled to the top of the board; a passive heat exchanger coupled to the top of the board and spaced from the integrated circuit component; at least one electronic component coupled to the printed circuit board below the top of the printed circuit board; and at least one heat pipe having an evaporator end adjacent the electronic component and extending away from the evaporator end along the bottom of the board to a condenser end above the top of the board, the condenser end being thermally coupled to the passive heat exchanger on the top of the board; wherein heat from electronic component is moved away from the electronic component and the integrated circuit component to the passive heat exchanger.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Inventors: Unnikrishnan VADAKKANMARU VEEDU, Silvia Anali SOTO DE LA TORRE, Alexander LYAKHOV, Krishna BHARATH, Fenghua SHEN, Madhavi TADEPALLI
  • Patent number: 11791528
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: October 17, 2023
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • Patent number: 11735535
    Abstract: Embodiments include an inductor, a method to form the inductor, and a semiconductor package. An inductor includes a plurality of plated-through-hole (PTH) vias in a substrate layer, and a plurality of magnetic interconnects with a plurality of openings in the substrate layer. The openings of the magnetic interconnects surround the PTH vias. The inductor also includes an insulating layer in the substrate layer, a first conductive layer over the PTH vias, magnetic interconnects, and insulating layer, and a second conductive layer below the PTH vias, magnetic interconnects, and insulating layer. The insulating layer surrounds the PTH vias and magnetic interconnects. The magnetic interconnects may have a thickness substantially equal to a thickness of the PTH vias. The magnetic interconnects may be shaped as hollow cylindrical magnetic cores with magnetic materials. The magnetic materials may include ferroelectric, conductive, or epoxy materials. The hollow cylindrical magnetic cores may be ferroelectric cores.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Kaladhar Radhakrishnan, Krishna Bharath, Clive Hendricks
  • Publication number: 20230244552
    Abstract: In some embodiments, an API specification document is processed to extract metadata representing API elements. Dependencies are mapped between the API elements using orders and ranks to create a metamodel that includes a map of metadata attributes and links that represent functional and operational aspects of program elements accessible via the API. The metamodel is stored for use in generating support infrastructure artifacts. In some embodiments, database entities are compared to a metamodel to generate matches. Each match indicates a confidence score and a relationship between a database entity and a metadata attribute. A selection of a metadata attribute is received for inclusion in the new API, and a selection of a database entity to be associated with the metadata attribute for the new API is received. The computing system updates the confidence score for the match that indicates the relationship between the database entity and the metadata attribute.
    Type: Application
    Filed: April 6, 2023
    Publication date: August 3, 2023
    Applicant: Conektto, Inc.
    Inventors: Amol Dewhare, Ramanathan Sathianarayanan, Krishna Bharath Kashyap
  • Patent number: 11688729
    Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Krishna Bharath, Mathew Manusharow
  • Publication number: 20230187407
    Abstract: A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 15, 2023
    Applicant: Intel Corporation
    Inventors: Carleton L. Molnar, Adel A. Elsherbini, Tanay Karnik, Shawna M. Liff, Robert J. Munoz, Julien Sebot, Johanna M. Swan, Nevine Nassif, Gerald S. Pasdast, Krishna Bharath, Neelam Chandwani, Dmitri E. Nikonov