Patents by Inventor Krishna Kumar Bhuwalka
Krishna Kumar Bhuwalka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9711632Abstract: The present disclosure relates to an intra-band tunnel FET, which has a symmetric FET that is able to provide for a high drive current. In some embodiments, the disclosed intra-band tunnel FET has a source region having a first doping type and a drain region having the first doping type. The source region and the drain region are separated by a channel region. A gate region may generate an electric field that varies the position of a valence band and/or a conduction band in the channel region. By controlling the position of the valence band and/or the conduction band of the channel region, quantum mechanical tunneling of charge carries between the conduction band in the source region and in the drain region or between the valence band in the source region and in the drain region can be controlled.Type: GrantFiled: April 16, 2013Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gerben Doornbos, Krishna Kumar Bhuwalka
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Patent number: 9647097Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.Type: GrantFiled: December 22, 2014Date of Patent: May 9, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
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Patent number: 9634092Abstract: Provided is a finFET device. The finFET device may include an active region which protrudes vertically from a substrate, a channel region disposed on a center of the active region, a drain region disposed on one side surface of the channel region, and a source region disposed on the other side surface of the channel region, a gate insulating layer formed on two opposing side surfaces of the channel region and having a U-shaped cross-section, gate spacers formed on outer surfaces of the gate insulating layer, drain spacers formed on two opposing side surfaces of the drain region, and source spacers formed on two opposing side surfaces of the source region, and at least one of the two side surfaces of the drain region has a tapered part.Type: GrantFiled: February 18, 2016Date of Patent: April 25, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Krishna Kumar Bhuwalka, Zhenhua Wu, Uihui Kwon, Keunho Lee
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Publication number: 20160300911Abstract: Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.Type: ApplicationFiled: June 22, 2016Publication date: October 13, 2016Inventors: Martin Christopher Holland, Georgios Vellianitis, Richard Kenneth Oxland, Krishna Kumar Bhuwalka, Gerben Doornbos
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Publication number: 20160254348Abstract: Provided is a finFET device. The finFET device may include an active region which protrudes vertically from a substrate, a channel region disposed on a center of the active region, a drain region disposed on one side surface of the channel region, and a source region disposed on the other side surface of the channel region, a gate insulating layer formed on two opposing side surfaces of the channel region and having a U-shaped cross-section, gate spacers formed on outer surfaces of the gate insulating layer, drain spacers formed on two opposing side surfaces of the drain region, and source spacers formed on two opposing side surfaces of the source region, and at least one of the two side surfaces of the drain region has a tapered part.Type: ApplicationFiled: February 18, 2016Publication date: September 1, 2016Inventors: Krishna Kumar BHUWALKA, Zhenhua WU, Uihui KWON, Keunho LEE
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Patent number: 9419114Abstract: A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region. The TFET further comprises a drain region contacting the channel region, wherein the source region and the drain region are of opposite conductivity type. The TFET also comprises a pocket layer covering a gate interface portion of the source region and contacting at least part of the channel region. The TFET further comprises a gate dielectric layer covering the pocket layer and a gate electrode covering the gate dielectric layer. The gate interface portion of the source region comprises at least three mutually non-coplanar surface segments. A method for manufacturing such a TFET device is also provided.Type: GrantFiled: January 16, 2015Date of Patent: August 16, 2016Assignees: IMEC VZW, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Amey Mahadev Walke, Anne VanDooren, Krishna Kumar Bhuwalka
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Patent number: 9412871Abstract: A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs.Type: GrantFiled: March 8, 2013Date of Patent: August 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gerben Doornbos, Mark van Dal, Georgios Vellianitis, Blandine Duriez, Krishna Kumar Bhuwalka, Richard Kenneth Oxland, Martin Christopher Holland, Yee-Chaung See, Matthias Passlack
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Patent number: 9385198Abstract: Various heterostructures and methods of forming heterostructures are disclosed. A structure includes a substrate, a template layer, a barrier layer, and a device layer. The substrate comprises a first crystalline material. The template layer comprises a second crystalline material, and the second crystalline material is lattice mismatched to the first crystalline material. The template layer is over and adjoins the first crystalline material, and the template layer is at least partially disposed in an opening of a dielectric material. The barrier layer comprises a third crystalline material, and the third crystalline material is a binary III-V compound semiconductor. The barrier layer is over the template layer. The device layer comprises a fourth crystalline material, and the device layer is over the barrier layer.Type: GrantFiled: May 15, 2013Date of Patent: July 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Martin Christopher Holland, Georgios Vellianitis, Richard Kenneth Oxland, Krishna Kumar Bhuwalka, Gerben Doornbos
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Patent number: 9368353Abstract: A method comprises growing a channel layer comprising a first channel region and a second channel region, depositing a first hard mask layer over the channel layer, patterning the first hard mask layer, applying a first delta doping process to the first channel region to form a first delta doping layer over the first channel region, depositing a first cap layer over the first delta doping layer, depositing a second hard mask layer over the channel layer, wherein the first cap layer is embedded in the second hard mask layer, patterning the second hard mask layer and the first hard mask layer to expose the second channel region, applying a second delta doping process to the second channel region to form a second delta doping layer over the second channel region and applying a first diffusion process to the first delta doping layer and the second delta doping layer.Type: GrantFiled: June 10, 2015Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Krishna Kumar Bhuwalka, Martin Christopher Holland
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Patent number: 9337109Abstract: A multi-threshold voltage (Vt) field-effect transistor (FET) formed through strain engineering is provided. An embodiment integrated circuit device includes a first transistor including a first channel region over a first buffer, the first channel region formed from a III-V semiconductor material and a second transistor including a second channel region over a second buffer, the second channel region formed from the III-V semiconductor material, the second buffer and the first buffer having a lattice mismatch. A first strain introduced by a lattice mismatch between the III-V semiconductor material and the first buffer is different than a second strain introduced by a lattice mismatch between the III-V semiconductor material and the second buffer. Therefore, the threshold voltage of the first transistor is different than the threshold voltage of the second transistor.Type: GrantFiled: May 24, 2013Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gerben Doornbos, Krishna Kumar Bhuwalka
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Publication number: 20160118475Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region.Type: ApplicationFiled: December 30, 2015Publication date: April 28, 2016Inventors: Richard Kenneth Oxland, Martin Christopher Holland, Krishna Kumar Bhuwalka
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Patent number: 9231102Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region.Type: GrantFiled: August 29, 2013Date of Patent: January 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Richard Kenneth Oxland, Martin Christopher Holland, Krishna Kumar Bhuwalka
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Publication number: 20150279679Abstract: A method comprises growing a channel layer comprising a first channel region and a second channel region, depositing a first hard mask layer over the channel layer, patterning the first hard mask layer, applying a first delta doping process to the first channel region to form a first delta doping layer over the first channel region, depositing a first cap layer over the first delta doping layer, depositing a second hard mask layer over the channel layer, wherein the first cap layer is embedded in the second hard mask layer, patterning the second hard mask layer and the first hard mask layer to expose the second channel region, applying a second delta doping process to the second channel region to form a second delta doping layer over the second channel region and applying a first diffusion process to the first delta doping layer and the second delta doping layer.Type: ApplicationFiled: June 10, 2015Publication date: October 1, 2015Inventors: Krishna Kumar Bhuwalka, Martin Christopher Holland
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Patent number: 9093273Abstract: A method comprises growing a channel layer over a substrate, wherein the channel layer comprises a first channel region and a second channel region, and wherein the first channel region and the second channel region are separated by a first isolation region, depositing a hard mask layer over the channel layer, patterning the hard mask layer, applying a first delta doping process to the first channel region to form a first delta doping layer over the first channel region, applying a second delta doping process to the second channel region to form a second delta doping layer over the second channel region, wherein the second delta doping layer is of a different doping density from the first delta doping layer and applying a diffusion process to the first delta doping layer and the second delta doping layer.Type: GrantFiled: August 23, 2013Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Krishna Kumar Bhuwalka, Martin Christopher Holland
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Publication number: 20150206958Abstract: A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region. The TFET further comprises a drain region contacting the channel region, wherein the source region and the drain region are of opposite conductivity type. The TFET also comprises a pocket layer covering a gate interface portion of the source region and contacting at least part of the channel region. The TFET further comprises a gate dielectric layer covering the pocket layer and a gate electrode covering the gate dielectric layer. The gate interface portion of the source region comprises at least three mutually non-coplanar surface segments. A method for manufacturing such a TFET device is also provided.Type: ApplicationFiled: January 16, 2015Publication date: July 23, 2015Inventors: Amey Mahadev Walke, Anne VanDooren, Krishna Kumar Bhuwalka
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Publication number: 20150137079Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.Type: ApplicationFiled: December 22, 2014Publication date: May 21, 2015Inventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
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Publication number: 20150061005Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Richard Kenneth Oxland, Martin Christopher Holland, Krishna Kumar Bhuwalka
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Publication number: 20150054120Abstract: A method comprises growing a channel layer over a substrate, wherein the channel layer comprises a first channel region and a second channel region, and wherein the first channel region and the second channel region are separated by a first isolation region, depositing a hard mask layer over the channel layer, patterning the hard mask layer, applying a first delta doping process to the first channel region to form a first delta doping layer over the first channel region, applying a second delta doping process to the second channel region to form a second delta doping layer over the second channel region, wherein the second delta doping layer is of a different doping density from the first delta doping layer and applying a diffusion process to the first delta doping layer and the second delta doping layer.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Krishna Kumar Bhuwalka, Martin Christopher Holland
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Publication number: 20140346564Abstract: A multi-threshold voltage (Vt) field-effect transistor (FET) formed through strain engineering is provided. An embodiment integrated circuit device includes a first transistor including a first channel region over a first buffer, the first channel region formed from a III-V semiconductor material and a second transistor including a second channel region over a second buffer, the second channel region formed from the III-V semiconductor material, the second buffer and the first buffer having a lattice mismatch. A first strain introduced by a lattice mismatch between the III-V semiconductor material and the first buffer is different than a second strain introduced by a lattice mismatch between the III-V semiconductor material and the second buffer. Therefore, the threshold voltage of the first transistor is different than the threshold voltage of the second transistor.Type: ApplicationFiled: May 24, 2013Publication date: November 27, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gerben Doornbos, Krishna Kumar Bhuwalka
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Publication number: 20140264277Abstract: The present disclosure relates to an intra-band tunnel FET, which has a symmetric FET that is able to provide for a high drive current. In some embodiments, the disclosed intra-band tunnel FET has a source region having a first doping type and a drain region having the first doping type. The source region and the drain region are separated by a channel region. A gate region may generate an electric field that varies the position of a valence band and/or a conduction band in the channel region. By controlling the position of the valence band and/or the conduction band of the channel region, quantum mechanical tunneling of charge carries between the conduction band in the source region and in the drain region or between the valence band in the source region and in the drain region can be controlled.Type: ApplicationFiled: April 16, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gerben Doornbos, Krishna Kumar Bhuwalka