Patents by Inventor Krishna Kumar Bhuwalka

Krishna Kumar Bhuwalka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140264438
    Abstract: Various heterostructures and methods of forming heterostructures are disclosed. A structure includes a substrate, a template layer, a barrier layer, and a device layer. The substrate comprises a first crystalline material. The template layer comprises a second crystalline material, and the second crystalline material is lattice mismatched to the first crystalline material. The template layer is over and adjoins the first crystalline material, and the template layer is at least partially disposed in an opening of a dielectric material. The barrier layer comprises a third crystalline material, and the third crystalline material is a binary III-V compound semiconductor. The barrier layer is over the template layer. The device layer comprises a fourth crystalline material, and the device layer is over the barrier layer.
    Type: Application
    Filed: May 15, 2013
    Publication date: September 18, 2014
    Inventors: Martin Christopher Holland, Georgios Vellianitis, Richard Kenneth Oxland, Krishna Kumar Bhuwalka, Gerben Doornbos
  • Publication number: 20140252478
    Abstract: A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Inventors: Gerben Doornbos, Mark van Dal, Georgios Vellianitis, Blandine Duriez, Krishna Kumar Bhuwalka, Richard Kenneth Oxland, Martin Christopher Holland, Yee-Chaung See, Matthias Passlack
  • Patent number: 8802531
    Abstract: A Fin Field-Effect Transistor (FinFET) includes a fin, which includes a channel splitter having a first bandgap, and a channel including a first portion and a second portion on opposite sidewalls of the channel splitter. The channel has a second bandgap smaller than the first bandgap. A gate electrode includes a first portion and a second portion on opposite sides of the fin. A gate insulator includes a first portion between the first portion of the gate electrode and the first portion of the channel, and a second portion between the second portion of the gate electrode and the second portion of the channel.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
  • Patent number: 8723223
    Abstract: A hybrid Fin Field-Effect Transistor (FinFET) includes a first and a second FinFET. The first FinFET includes a first channel region formed of a first semiconductor fin, and a first source region and a first drain region of a first conductivity type. The second FinFET includes a second channel region formed of a second semiconductor fin, a second source region of a second conductivity type opposite the first conductivity type, and a second drain region of the first conductivity type. The second source region and the second drain region are connected to opposite ends of the second channel region. The first and the second gate electrodes are interconnected. The first and the second source regions are electrically interconnected. The first and the second drain regions are electrically interconnected.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: May 13, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Krishna Kumar Bhuwalka
  • Patent number: 8697510
    Abstract: A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Ken-Ichi Goto
  • Patent number: 8669163
    Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Ching-Ya Wang, Ken-Ichi Goto, Wen-Chin Lee, Carlos H. Diaz
  • Publication number: 20140065780
    Abstract: A Fin Field-Effect Transistor (FinFET) includes a fin, which includes a channel splitter having a first bandgap, and a channel including a first portion and a second portion on opposite sidewalls of the channel splitter. The channel has a second bandgap smaller than the first bandgap. A gate electrode includes a first portion and a second portion on opposite sides of the fin. A gate insulator includes a first portion between the first portion of the gate electrode and the first portion of the channel, and a second portion between the second portion of the gate electrode and the second portion of the channel.
    Type: Application
    Filed: November 13, 2013
    Publication date: March 6, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
  • Patent number: 8614468
    Abstract: A device includes a first source/drain region of a first conductivity type over a silicon substrate, wherein the first source/drain region is at a higher step of a two-step profile. The first source/drain region includes a germanium-containing region. A second source/drain region is of a second conductivity type opposite the first conductivity type, wherein the second source/drain region is at a lower step of the two-step profile. A gate dielectric includes a vertical portion in contact with a side edge the silicon substrate, and a horizontal portion in contact with a top surface of the silicon substrate at the lower step. The horizontal portion is connected to a lower end of the vertical portion. A gate electrode is directly over the horizontal portion, wherein a sidewall of the gate electrode is in contact with the vertical portion of the gate dielectric.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: December 24, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mark van Dal, Krishna Kumar Bhuwalka
  • Patent number: 8604518
    Abstract: A Fin Field-Effect Transistor (FinFET) includes a fin, which includes a channel splitter having a first bandgap, and a channel including a first portion and a second portion on opposite sidewalls of the channel splitter. The channel has a second bandgap smaller than the first bandgap. A gate electrode includes a first portion and a second portion on opposite sides of the fin. A gate insulator includes a first portion between the first portion of the gate electrode and the first portion of the channel, and a second portion between the second portion of the gate electrode and the second portion of the channel.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: December 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
  • Patent number: 8587075
    Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; and a gate electrode over the gate dielectric. A first source/drain region is adjacent the gate dielectric, wherein the first source/drain region is a semiconductor region and of a first conductivity type. A second source/drain region is on an opposite side of the channel region than the first source/drain region, wherein the second source/drain region is a metal region. A pocket region of a second conductivity type opposite the first conductivity type is horizontally between the channel region and the second source/drain region.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Yi-Ming Sheu, Carlos H. Diaz
  • Publication number: 20130270607
    Abstract: A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 17, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gerben Doornbos, Krishna Kumar Bhuwalka, Matthias Passlack
  • Patent number: 8471329
    Abstract: A tunnel field-effect transistor (TFET) includes a gate electrode, a source region, and a drain region. The source and drain regions are of opposite conductivity types. A channel region is disposed between the source region and the drain region. A source diffusion barrier is disposed between the channel region and the source region. The source diffusion barrier and the source region are under and overlapping the gate electrode. The source diffusion barrier has a first bandgap greater than second bandgaps of the source region, the drain region, and the channel region.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: June 25, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
  • Publication number: 20130134481
    Abstract: A Fin Field-Effect Transistor (FinFET) includes a fin, which includes a channel splitter having a first bandgap, and a channel including a first portion and a second portion on opposite sidewalls of the channel splitter. The channel has a second bandgap smaller than the first bandgap. A gate electrode includes a first portion and a second portion on opposite sides of the fin. A gate insulator includes a first portion between the first portion of the gate electrode and the first portion of the channel, and a second portion between the second portion of the gate electrode and the second portion of the channel.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
  • Publication number: 20130134522
    Abstract: A hybrid Fin Field-Effect Transistor (FinFET) includes a first and a second FinFET. The first FinFET includes a first channel region formed of a first semiconductor fin, and a first source region and a first drain region of a first conductivity type. The second FinFET includes a second channel region formed of a second semiconductor fin, a second source region of a second conductivity type opposite the first conductivity type, and a second drain region of the first conductivity type. The second source region and the second drain region are connected to opposite ends of the second channel region. The first and the second gate electrodes are interconnected. The first and the second source regions are electrically interconnected. The first and the second drain regions are electrically interconnected.
    Type: Application
    Filed: May 4, 2012
    Publication date: May 30, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Krishna Kumar Bhuwalka
  • Publication number: 20130119395
    Abstract: A tunnel field-effect transistor (TFET) includes a gate electrode, a source region, and a drain region. The source and drain regions are of opposite conductivity types. A channel region is disposed between the source region and the drain region. A source diffusion barrier is disposed between the channel region and the source region. The source diffusion barrier and the source region are under and overlapping the gate electrode. The source diffusion barrier has a first bandgap greater than second bandgaps of the source region, the drain region, and the channel region.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 16, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
  • Patent number: 8354695
    Abstract: A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: January 15, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Ken-Ichi Goto
  • Publication number: 20120319167
    Abstract: A device includes a first source/drain region of a first conductivity type over a silicon substrate, wherein the first source/drain region is at a higher step of a two-step profile. The first source/drain region includes a germanium-containing region. A second source/drain region is of a second conductivity type opposite the first conductivity type, wherein the second source/drain region is at a lower step of the two-step profile. A gate dielectric includes a vertical portion in contact with a side edge the silicon substrate, and a horizontal portion in contact with a top surface of the silicon substrate at the lower step. The horizontal portion is connected to a lower end of the vertical portion. A gate electrode is directly over the horizontal portion, wherein a sidewall of the gate electrode is in contact with the vertical portion of the gate dielectric.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mark van Dal, Krishna Kumar Bhuwalka
  • Publication number: 20110027959
    Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.
    Type: Application
    Filed: October 5, 2010
    Publication date: February 3, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Ching-Ya Wang, Ken-Ichi Goto, Wen-Chin Lee, Carlos H. Diaz
  • Publication number: 20100327321
    Abstract: A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions.
    Type: Application
    Filed: September 13, 2010
    Publication date: December 30, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Ken-Ichi Goto
  • Patent number: 7834345
    Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: November 16, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Ching-Ya Wang, Ken-Ichi Goto, Wen-Chin Lee, Carlos H. Diaz