Abstract: An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit.

Abstract: A message channel optimization method and system enables multi-flow access to the message channel infrastructure within a CPU of a processor-based system. A user (pcode) employs a virtual channel to submit message channel transactions, with the message channel driver processing the transaction “behind the scenes”. The message channel driver thus allows the user to continue processing without having to block other transactions from being processed. Each transaction will be processed, either immediately or at some future time, by the message channel driver. The message channel optimization method and system are useful for tasks involving message channel transactions as well as non-message channel transactions.

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

Abstract: Methods and systems may provide for identifying a workload associated with a platform and determining a scalability of the workload. Additionally, a performance policy of the platform may be managed based at least in part on the scalability of the workload. In one example, determining the scalability includes determining a ratio of productive cycles to actual cycles.

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

Abstract: A message channel optimization method and system enables multi-flow access to the message channel infrastructure within a CPU of a processor-based system. A user (pcode) employs a virtual channel to submit message channel transactions, with the message channel driver processing the transaction “behind the scenes”. The message channel driver thus allows the user to continue processing without having to block other transactions from being processed. Each transaction will be processed, either immediately or at some future time, by the message channel driver. The message channel optimization method and system are useful for tasks involving message channel transactions as well as non-message channel transactions.

Abstract: In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed.

Abstract: Wear-out equalization techniques for multiple functional hardware units are disclosed. An integrated circuit includes a power control unit (PCU) configured to monitor indicators of wear-out incurred by multiple functional hardware units of the integrated circuit. The PCU calculates cumulative wear-out metrics of the functional hardware units based on the monitored indicators and performs an equalization action to equalize the cumulative wear-out metrics of the functional hardware units.

Abstract: In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed.

Abstract: Apparatus, systems, and methods to manage memory operations are described. In one embodiment, a controller is coupled to a processor unit, and comprising logic to block additional transactions on the processor unit, initiate a cache flush to flush data from cache memory coupled to the processor unit to a memory controller buffer, block incoming data from the cache memory, and initiate a buffer flush to flush data from the memory controller buffer to a nonvolatile memory. Other examples are also disclosed and claimed.

Abstract: Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, a link width modulation logic adjusts the width of an interconnect link. More particularly, the link width modulation logic causes the interconnect link to transition from a first width to a second width based on comparison of a utilization value associated with the interconnect link against at least one of a plurality of utilization threshold values. Other embodiments are also disclosed and claimed.

Abstract: An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.

Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Abstract: An event management resource monitors a processor environment. In response to detecting occurrence of a trigger event in the processor environment, the event management resource initiates a transfer of processor cache data from volatile storage in the processor environment to non-volatile memory. The event management resource can be configured to produce status information associated with the transfer of cache data to a respective non-volatile memory resource. The event management resource stores the status information in a non-volatile storage resource for later retrieval. Accordingly, status information associated with the event causing the transfer is available for analysis on subsequent power up or reboot of a respective computer system.

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a cache memory including a plurality of portions distributed across a die of the processor, a plurality of sleep circuits each coupled to one of the portions of the cache memory, and at least one sleep control logic coupled to the cache memory portions to dynamically determine a sleep setting independently for each of the sleep circuits and to enable the corresponding sleep circuit to maintain the corresponding cache memory portion at a retention voltage. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.

Abstract: An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.

Abstract: A processor is described having a semiconductor chip having non volatile storage circuitry. The non volatile storage circuitry has information identifying a maximum operational frequency of the processor at which the processor's operation is guaranteed for an ambient temperature that corresponds to an extreme thermal event.

Abstract: A scalability algorithm causes a processor to initialize a performance indicator counter, operate at an initial frequency of the first clock signal for a first duration, and determine, based on the performance indicator counter, an initial performance of the first processing core. The algorithm may then cause the processor to operate at a second frequency of the first clock signal for a second duration and determine, based on the performance indicator counter, a second performance of the first processing core. A performance scalability of the first processing core may be determined based on the initial performance and the second performance and an operational parameter, such as one or more clock frequencies and/or supply voltage(s), may be changed based on the determined scalability.

Abstract: In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed.