Patents by Inventor Krishnakanth V. Sistla

Krishnakanth V. Sistla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Changing the clock frequency of a computing device
    Patent number: 9660799
    Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Ernest Knoll, Ofer Nathan, Michael Mishaeli, Krishnakanth V. Sistla, Ariel Sabba, Shani Rehana, Ariel Szapiro, Tsvika Kurts, Ofer Levy
  • MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS
    Publication number: 20170115716
    Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.
    Type: Application
    Filed: August 16, 2016
    Publication date: April 27, 2017
    Inventors: ANKUSH VARMA, KRISHNAKANTH V. SISTLA, MARTIN T. ROWLAND, CHRIS POIRIER, ERIC J. DEHAEMER, AVINASH N. ANANTHAKRISHNAN, JEREMY J. SHRALL, XIUTING C. MAN, STEPHEN H. GUNTHER, KRISHNA K. RANGAN, DEVADATTA V. BODAS, DON SOLTIS, HANG T. NGUYEN, CYPRIAN W. WOO, THI DANG
  • Forcing Core Low Power States In A Processor
    Publication number: 20170102752
    Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.
    Type: Application
    Filed: October 18, 2016
    Publication date: April 13, 2017
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Allen W. Chu, Ian M. Steiner
  • User Level Control Of Power Management Policies
    Publication number: 20170083076
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • MASKING A POWER STATE OF A CORE OF A PROCESSOR
    Publication number: 20170031412
    Abstract: In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.
    Type: Application
    Filed: July 29, 2015
    Publication date: February 2, 2017
    Inventors: Alexander Gendler, Larisa Novakovsky, Krishnakanth V. Sistla, Vivek Garg, Dean Mulla, Ashish V. Choubal, Erik G. Hallnor, Kimberly C. Weier
  • Dynamic power limit sharing in a platform
    Patent number: 9557804
    Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 31, 2017
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Cesar A. Quiroz, Vivek Garg, Martin T. Rowland, Inder M. Sodhi, James S. Burns
  • OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU
    Publication number: 20170017286
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: September 30, 2016
    Publication date: January 19, 2017
    Inventors: YEN-CHENG LIU, P. KEONG OR, KRISHNAKANTH V. SISTLA, GANAPATI SRINIVASA
  • OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU
    Publication number: 20170017292
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: September 30, 2016
    Publication date: January 19, 2017
    Inventors: YEN-CHENG LIU, P. KEONG OR, KRISHNAKANTH V. SISTLA, GANAPATI SRINIVASA
  • Dynamically measuring power consumption in a processor
    Patent number: 9547027
    Abstract: In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: January 17, 2017
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Vivek Garg, James S. Burns
  • COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT
    Publication number: 20170003724
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Application
    Filed: September 12, 2016
    Publication date: January 5, 2017
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
  • User level control of power management policies
    Patent number: 9535487
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: January 3, 2017
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • TRACKING MISSED PERIODIC ACTIONS ACROSS STATE DOMAINS
    Publication number: 20160378173
    Abstract: Systems and methods may provide for determining, in a first domain that manages a state of a second domain, that the second domain is in the state and determining, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state. Additionally, the periodic action may be documented as a missed event with respect to the second domain. In one example, documenting the periodic action as a missed event includes incrementing a missed event counter.
    Type: Application
    Filed: June 27, 2015
    Publication date: December 29, 2016
    Applicant: INTEL CORPORATION
    Inventors: Dean Mulla, Daniel G. Borkowski, Krishnakanth V. Sistla, Victor Wu, Manev Luthra
  • METHOD AND APPARATUS FOR EXECUTION MODE SELECTION
    Publication number: 20160378486
    Abstract: An apparatus and method for performing high performance instruction emulation. For example, one embodiment of the invention includes a processor to process an instruction set including high-power and standard instructions comprising: an analysis module to determine whether a number of high-power instructions within a specified window are above or below a specified threshold; an execution mode selection module to select a native execution of the high-power instructions if the number of high-power instructions are above the specified threshold or to select an emulated execution of the high-powered instructions if the number of high-power instructions are below the specified threshold.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: ANKUSH VARMA, KRISTOFFER D. FLEMING, EUGENE GORBATOV, ROBERT E. GOUGH, KRISHNAKANTH V. SISTLA
  • Measurement of performance scalability in a microprocessor
    Patent number: 9513688
    Abstract: A scalability algorithm causes a processor to initialize a performance indicator counter, operate at an initial frequency of the first clock signal for a first duration, and determine, based on the performance indicator counter, an initial performance of the first processing core. The algorithm may then cause the processor to operate at a second frequency of the first clock signal for a second duration and determine, based on the performance indicator counter, a second performance of the first processing core. A performance scalability of the first processing core may be determined based on the initial performance and the second performance and an operational parameter, such as one or more clock frequencies and/or supply voltage(s), may be changed based on the determined scalability.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Jeremy J. Shrall, Avinash N. Ananthakrishnan
  • Forcing core low power states in a processor
    Patent number: 9495001
    Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Allen W. Chu, Ian M. Steiner
  • Processor having frequency of operation information for guaranteed operation under high temperature events
    Patent number: 9494996
    Abstract: A processor is described having a semiconductor chip having non volatile storage circuitry. The non volatile storage circuitry has information identifying a maximum operational frequency of the processor at which the processor's operation is guaranteed for an ambient temperature that corresponds to an extreme thermal event.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Robin A. Steinbrecher, Susan F. Smith, Sandeep Ahuja, Vivek Garg, Tessil Thomas, Krishnakanth V. Sistla, Chris Poirier, Martin Mark T. Rowland
  • Collaborative processor and system performance and power management
    Patent number: 9454379
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: September 27, 2016
    Assignee: Intel Corporation
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
  • Dynamically Modifying A Power/Performance Tradeoff Based On A Processor Utilization
    Publication number: 20160266941
    Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
    Type: Application
    Filed: May 24, 2016
    Publication date: September 15, 2016
    Inventors: Krishnakanth V. Sistla, Mark Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Daniel Borkowski, Vivek Garg, Cagdas Akturan, Avinash N. Ananthakrishnan
  • Collaborative processor and system performance and power management
    Patent number: 9442739
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
  • SUPERCAPACITOR-BASED POWER SUPPLY PROTECTION FOR MULTI-NODE SYSTEMS
    Publication number: 20160252942
    Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 1, 2016
    Inventors: Ankush Varma, Vasudevan Srinivasan, Eugene Gorbatov, Andrew D. Henroid, Barnes Cooper, David W. Browning, Guy M. Therien, Neil W. Songer, Krishnakanth V. Sistla, James G. Hermerding, II