Patents by Inventor Krishnakanth V. Sistla

Krishnakanth V. Sistla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DYNAMICALLY UPDATING LOGICAL IDENTIFIERS OF CORES OF A PROCESSOR
    Publication number: 20160252943
    Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 1, 2016
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Guy G. Sotomayor, Andrew D. Henroid, Robert E. Gough, Tod F. Schiff
  • PERFORMING DYNAMIC POWER CONTROL OF PLATFORM DEVICES
    Publication number: 20160239068
    Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.
    Type: Application
    Filed: February 17, 2015
    Publication date: August 18, 2016
    Inventors: ANKUSH VARMA, KRISHNAKANTH V. SISTLA, VASUDEVAN SRINIVASAN, EUGENE GORBATOV, ANDREW D. HENROID, BARNES COOPER, DAVID W. BROWNING, GUY M. THERIEN, NEIL W. SONGER, JAMES G. HERMERDING, II
  • Mechanism to provide workload and configuration-aware deterministic performance for microprocessors
    Patent number: 9417681
    Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don Soltis, Hang T. Nguyen, Cyprian W. Woo, Thi Dang
  • Performing frequency coordination in a multiprocessor system
    Patent number: 9405351
    Abstract: In an embodiment, a processor includes a core to execute instructions, uncore logic coupled to the core, and a power controller to control a power consumption level. The power controller is configured to determine an activity level of the processor and responsive to this level, to generate a request for communication to a second processor coupled to the processor to request frequency coordination between the processors. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Ian M. Steiner, Vivek Garg, Chris Poirier, Martin T. Rowland
  • OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU
    Publication number: 20160195913
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: December 17, 2015
    Publication date: July 7, 2016
    Inventors: YEN-CHENG LIU, P. KEONG OR, KRISHNAKANTH V. SISTLA, GANAPATI SRINIVASA
  • METHOD AND APPARATUS TO CONTROL A LINK POWER STATE
    Publication number: 20160187952
    Abstract: A method is provided for controlling a link. This may include determining a condition of a first device coupled to the link, receiving, at the first device, a request for a specific link state from a second device coupled to the link, and determining a power state of the link based on the determined condition of the first device.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Inventors: Corey D. Gough, Ian M. Steiner, Krishnakanth V. Sistla
  • APPARATUS AND METHOD TO PROVIDE A THERMAL PARAMETER REPORT FOR A MULTI-CHIP PACKAGE
    Publication number: 20160179158
    Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.
    Type: Application
    Filed: September 14, 2015
    Publication date: June 23, 2016
    Inventors: Tessil Thomas, Robin A. Steinbrecher, Sandeep Ahuja, Michael Berktold, Timothy Y. Kam, Howard Chin, Phani Kumar Kandula, Krishnakanth V. Sistla
  • Dynamically modifying a power/performance tradeoff based on processor utilization
    Patent number: 9372524
    Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Mark Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Daniel Borkowski, Vivek Garg, Cagdas Akturan, Avinash N. Ananthakrishnan
  • Optimizing power usage by factoring processor architectural events to PMU
    Patent number: 9367112
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: June 14, 2016
    Assignee: INTEL CORPORATION
    Inventors: Yen-Cheng Liu, P. Keong Or, Krishnakanth V. Sistla, Ganapati Srinivasa
  • Utilization-aware low-overhead link-width modulation for power reduction in interconnects
    Patent number: 9336175
    Abstract: Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, link width modulation logic adjusts the width of an interconnect link. More particularly, the link width modulation logic causes the interconnect link to transition from a first width to a second width based on comparison of a utilization value associated with the interconnect link against at least one of a plurality of utilization threshold values. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 6, 2015
    Date of Patent: May 10, 2016
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Buck W. Gremel, Robert G. Blankenship, Krishnakanth V. Sistla, Michael F. Cole
  • Adaptively controlling low power mode operation for a cache memory
    Patent number: 9335814
    Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a cache memory including a plurality of portions distributed across a die of the processor, a plurality of sleep circuits each coupled to one of the portions of the cache memory, and at least one sleep control logic coupled to the cache memory portions to dynamically determine a sleep setting independently for each of the sleep circuits and to enable the corresponding sleep circuit to maintain the corresponding cache memory portion at a retention voltage. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: May 10, 2016
    Assignee: Intel Corporation
    Inventors: Stefan Rusu, Min Huang, Wei Chen, Krishnakanth V. Sistla
  • Apparatus and method for controlling the reliability stress rate on a processor
    Patent number: 9317389
    Abstract: An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 19, 2016
    Assignee: INTEL CORPORATION
    Inventors: Dorit Shapira, Krishnakanth V. Sistla, Efraim Rotem, Nadav Shulman, Shmulik Zobel, Allen Chu
  • Performing frequency coordination in a multiprocessor system based on response timing optimization
    Patent number: 9292468
    Abstract: In an embodiment, a processor includes a core to execute instructions and a logic to receive memory access requests from the core and to route the memory access requests to a local memory and to route snoop requests corresponding to the memory access requests to a remote processor. The logic is configured to maintain latency information regarding a difference between receipt of responses to the snoop requests from the remote processor and receipt of responses to the memory access requests from the local memory. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth V. Sistla
  • DYNAMIC POWER LIMIT SHARING IN A PLATFORM
    Publication number: 20160018883
    Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.
    Type: Application
    Filed: September 28, 2015
    Publication date: January 21, 2016
    Inventors: Ankush VARMA, Krishnakanth V. SISTLA, Cesar A. QUIROZ, Vivek GARG, Martin T. ROWLAND, Inder M. SODHI, James S. BURNS
  • User Level Control Of Power Management Policies
    Publication number: 20160004291
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Application
    Filed: September 16, 2015
    Publication date: January 7, 2016
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • APPARATUS AND METHOD FOR A USER CONFIGURABLE RELIABILITY CONTROL LOOP
    Publication number: 20150377955
    Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information from a user or manufacturer and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: Dorit Shapira, Krishnakanth V. Sistla, Efraim Rotem, Eric Distefano, James G. Hermerding, II, Esfir Natanzon
  • User level control of power management policies
    Patent number: 9170624
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: October 27, 2015
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • Dynamic power limit sharing in a platform
    Patent number: 9158351
    Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Cesar A. Quiroz, Vivek Garg, Martin T. Rowland, Inder M. Sodhi, James S. Burns
  • Controlling Configurable Peak Performance Limits Of A Processor
    Publication number: 20150286266
    Abstract: In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed.
    Type: Application
    Filed: June 18, 2015
    Publication date: October 8, 2015
    Inventors: Jeremy J. Shrall, Stephen H. Gunther, Krishnakanth V. Sistla, Ryan D. Wells, Shaun M. Conrad
  • UTILIZATION-AWARE LOW-OVERHEAD LINK-WIDTH MODULATION FOR POWER REDUCTION IN INTERCONNECTS
    Publication number: 20150269105
    Abstract: Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, link width modulation logic adjusts the width of an interconnect link. More particularly, the link width modulation logic causes the interconnect link to transition from a first width to a second width based on comparison of a utilization value associated with the interconnect link against at least one of a plurality of utilization threshold values. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 6, 2015
    Publication date: September 24, 2015
    Applicant: Intel Corporation
    Inventors: Ankush Varma, Buck W. Gremel, Robert G. Blankenship, Krishnakanth V. Sistla, Michael F. Cole