Abstract: A quadiature oscillator includes a master tuned oscillator and two injection-locked slave tuned oscillators.

Abstract: A baseband circuit having a transconductance filter (Gm-C filter) to receive a mixer signal. The Gm-C filter includes lossy integrators with coefficients for the filter to provide a filter frequency response that substantially replicates an ideal Gm-C filter.

Abstract: A device (200, FIG. 2) includes receive hardware (204) which performs analog-to-digital conversion. In accordance with an embodiment of the invention, the receive hardware includes a pipelined analog-to-digital converter (320, FIG. 3). Sample-and-hold circuitry (410, FIG. 4) associated with the analog-to-digital converter is configured (FIGS. 8, and 12-14) and switched (FIG. 7) in a manner that provides intermediate frequency to baseband downconversion and skew-insensitive double-sampling.

Abstract: An apparatus and system may include a microstrip line capable of being coupled to an amplifier, wherein the microstrip line is to transform an input impedance of the amplifier to a substantially resistive value, and wherein the microstrip line has a characteristic impedance approximately equal to a selected system reference impedance. The apparatus and system may include a transformer coupled to the microstrip line, wherein the transformer is to transform the substantially resistive value into approximately a resistance of a source impedance included in a source. An article may include data, which, when accessed, results in a machine performing a method including simulating selecting a system having a reference impedance and simulating coupling an amplifier having an input impedance to a source having a source impedance using a transformer coupled to a microstrip line.

Abstract: A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.

Abstract: A semiconductor cascode structure includes a plurality of source contacts located in a first diffusion region. The first diffusion region is substantially surrounded by a first gate region. The cascode structure also includes a plurality of drain contacts located in a second diffusion region. The second diffusion region is substantially surrounded by a second gate region.

Abstract: A semiconductor device or a circuit includes a controllable oscillator and circuitry that senses a voltage which may control the controllable oscillator and digitally controls a gain compensation, adaptively compensating for a drop in a gain against overall loop gain within a closed loop. In one embodiment, a single supply source may be used to power the closed loop while a variable gain stage that is digitally controllable may adjust the gain in a feed-forward manner based on the drop.

Abstract: A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

Abstract: Analog circuits for providing one or more waveform parameters, e.g., the DC offset or average, of an analog input signal. Separate biasing is not necessarily required. Some embodiments comprise field-effect-transistors (FETs) configured in various diode-connected configurations that take advantage of leakage currents through the FETs so that long resistors or large capacitors are not necessarily required. One embodiment comprises two diode-connected FETs to provide an unbiased DC offset voltage of an analog input signal.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.

Abstract: A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

Abstract: First and second oscillator cells include tank circuits that may be tuned to a desired resonant frequency using varactors as variable reactance devices in a phase-shifting network. First and second transformers are connected to the oscillator cells to control the varactors.

Abstract: In some embodiments, the invention includes an interconnect system having a single ended driver and a single ended hysteretic receiver. A single ended interconnect is coupled between the single ended driver and single ended receiver. In other embodiments, the invention involves an interconnect system including interconnects, single ended drivers, and single ended hysteretic receivers connected to respective ones of the interconnects. The single ended drivers receive respective data-in signals and an enable signal and wherein the drivers transmit interconnect signals on the interconnects when the enable signal is asserted. In yet other embodiments, the invention includes an interconnect system having interconnects, quasi-static drivers and receivers connected to respective ones of the interconnects.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

Abstract: A circuit including a clock signal input to receive a clock signal, at least one data signal input to receive at least one data signal, and a multiple input conditional inverter to receive the clock signal and the data signal, and to generate a dynamic output. The circuit also includes a conditional keeper circuit to charge a dynamic output node when the clock is evaluating and the dynamic output is high.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: A hierarchical clock distribution system includes a global clock grid that distributes a clock signal to a plurality of regional clock grids. Each of the regional clock grids then distributes the signal to a plurality of corresponding loads. The regional clock grids utilize salphasic clocking techniques to distribute the clock signal to the corresponding loads. The global grid achieves low skew based on the periodicity of the clock signal, rather than the dominance of a standing wave. The electrical distance to termination within the regional clock grids is preferably kept low to avoid the occurrence of phase change regions on the regional grids. In one approach, the regional grids are each driven at multiple points in a symmetrical fashion to reduce the electrical distance to termination.

Abstract: Methods and apparatus for generating a MOSFET based voltage reference circuit with automatic trimming of resistors to compensate for process and supply voltage variations and to improve the accuracy of a MOSFET based reference voltage circuit, a temperature compensated MOSFET based reference voltage, and arbitrary translation of the MOSFET based reference voltage with or without trimming are provided.