Patents by Inventor Krishnan Srinivasan

Krishnan Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8768654
    Abstract: Product data management systems, methods, and mediums. A method includes receiving PDM model and applying a template to the model. The method includes creating a description file based on the application of the template to the model. The method includes transferring the description file to a diagramming application. A diagram corresponding to the description file is created.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: July 1, 2014
    Assignee: Siemens Product Lifecycle Management Software Inc.
    Inventors: Krishnan Srinivasan, Narinder Nayar, Girish Kandi, Vinayak Pharande, Shailesh Charati, Manoj Vazarkar, Mehul Shah, Henry Lee Burks
  • Publication number: 20130226944
    Abstract: Data transformation can be performed across various data structures and formats. Moreover, data transformation can be format agnostic. Output data of a second structure can be generated as a function of input data of a first structure and a transform independent of the format of input and output data. In one instance, the transform can be specified by way of a graphical representation and encoded in a form independent of input and output data formats. Subsequently, data transformation can be performed as a function of the transform and input data.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: Microsoft Corporation
    Inventors: Sushil Baid, Kranthi K. Mannem, Palavalli R. Sharath, Anil K. Prasad, Siddharth Sharma, Krishnan Srinivasan
  • Publication number: 20130219009
    Abstract: A scalable data feed system is disclosed. The data feed system may be offered as a cloud service that can serve many enterprises or tenants that require data to be pulled from information sources such as FTP, POP3, databases, line of business systems, a topic subscription, or an RSS feed, and pushed the data to information sinks, such as SMTP, email, FTP, mobile phones, and other devices and services. A pull agent pumps data from pull sources and pushes the data out to push agent counterparts. The push agent transforms and sends the data in messages to push sink, such as FTP, SMTP, or a mobile device.
    Type: Application
    Filed: February 20, 2012
    Publication date: August 22, 2013
    Applicant: MICROSOFT CORPORATION
    Inventors: Anand Bheemarajaiah, Manas Garg, Sandeep Prabhu, Krishnan Srinivasan
  • Patent number: 8484397
    Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: July 9, 2013
    Assignee: Sonics, Inc.
    Inventors: Krishnan Srinivasan, Drew E. Wingard
  • Patent number: 8438320
    Abstract: Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: May 7, 2013
    Assignee: Sonics, Inc.
    Inventors: Krishnan Srinivasan, Drew E. Wingard, Chien-Chun Chou
  • Patent number: 8438306
    Abstract: A method, apparatus, and system for providing layer concurrency connecting two or more master Intellectual Property cores to a Network on a Chip (NoC) for an integrated circuit is provided. An embodiment includes two masters connected using a common tightly coupled protocol to a first interface of an NoC. A protocol conversion unit can be coupled between the two or more masters and the NoC to convert a request in the tightly coupled protocol to a decoupled protocol that decouples request phasing from response phasing and then passes the request in the decoupled protocol format onto the NoC. The system also provides for arbitration amongst the two or more masters. Requests from the masters are still in the common tightly coupled protocol and are translated by the protocol conversion unit into a request in a decoupled protocol to enable out of order return of responses.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: May 7, 2013
    Assignee: Sonics, Inc.
    Inventors: Benoit De Lescure, Krishnan Srinivasan
  • Publication number: 20120278046
    Abstract: Product data management systems, methods, and mediums. A method includes receiving PDM model and applying a template to the model. The method includes creating a description file based on the application of the template to the model. The method includes transferring the description file to a diagramming application. A diagram corresponding to the description file is created.
    Type: Application
    Filed: September 27, 2011
    Publication date: November 1, 2012
    Applicant: SIEMENS PRODUCT LIFECYCLE MANAGEMENT SOFTWARE INC.
    Inventors: Krishnan Srinivasan, Narinder Nayar, Girish Kandi, Vinayak Pharande, Shailesh Charati, Manoj Vazarkar, Mehul Shah, Henry Lee Burks
  • Publication number: 20120278277
    Abstract: Product Data Management systems, methods, and mediums. A method includes receiving a document component that includes business objects. The method includes receiving a document automation component. The method includes reading a document management part of the document component, and constructing a document model based on the document management part.
    Type: Application
    Filed: September 27, 2011
    Publication date: November 1, 2012
    Applicant: SIEMENS PRODUCT LIFECYCLE MANAGEMENT SOFTWARE INC.
    Inventors: Niranjan Dilip Marathe, Krishnan Srinivasan, Sarang Shashikant Bapat
  • Patent number: 8229723
    Abstract: Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design. A method for providing performance instrumentation and analysis of the electronic design includes defining a first and second set of intended software instrumentation test points and an associated first and second set of performance analysis units. The method further includes instrumenting the first and second sets of software instrumentation test points and the associated first and second sets of performance analysis units to a first model and a second model, respectively. The method further includes creating a first and a second set of software instances associated with the first and second sets of intended software instrumentation test points and associated sets of performance analysis units during run time of a first simulation and a second simulation of the electronic design associated with the first model and second model, respectively.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: July 24, 2012
    Assignee: Sonics, Inc.
    Inventors: Krishnan Srinivasan, Chien-Chun Chou, Drew Wingard
  • Patent number: 8214847
    Abstract: The present invention extends to methods, systems, and computer program products for configuring assurances within distributed messaging systems. A defined set of message log and cursor components are configurably activatable and deactivatable to compose a variety of different capture assurances, transfer assurances, and delivery assurances within a distributed messaging system. A composition of a capture assurance, a transfer assurance, and a delivery assurance can provide an end-to-end assurance for a messaging system. End-to-end assurances can include one of best effort, at-most-once, at-least-once, and exactly once and can include one of: durable or non-durable. Using a defined set of activatable and deactivatable message log and cursor components facilities more efficient transitions between desired assurances. In some embodiments, a composition of a capture assurance, a transfer assurance, and a delivery assurance provides durable exactly-once message delivery.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: July 3, 2012
    Assignee: Microsoft Corporation
    Inventors: Gueorgui Chkodrov, Richard D. Hill, Craig A. Critchley, Krishnan Srinivasan, Tihomir Tarnavski, Mitchell G. Morris, Pramod Gurunath
  • Patent number: 8200836
    Abstract: The present invention extends to methods, systems, and computer program products for durable exactly once message delivery at scale. A message capture system uses a synchronous capture channel and transactions to provide durable exactly once message capture. Messages are sent from the message capture system to a message delivery system over a network using an at least once transfer protocol. The message delivery system implements a durable at most once messaging behavior, the combination of which results in durable exactly once transfer of messages from the message capture system to the message delivery system. The message delivery system uses a synchronous delivery channel and transactions to provide durable exactly once message delivery. Cursors maintaining message consumer state are collocated with message consumers, freeing up message log resources to process increased volumes of messages, such as, for example, in a queued or pub/sub environment.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: June 12, 2012
    Assignee: Microsoft Corporation
    Inventors: Gueorgui Chkodrov, Richard D. Hill, Craig A. Critchley, Krishnan Srinivasan, Tihomir Tarnavski, Mitchell G. Morris, Pramod Gurunath
  • Patent number: 8190804
    Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: May 29, 2012
    Assignee: Sonics, Inc.
    Inventors: Krishnan Srinivasan, Drew E. Wingard
  • Publication number: 20120110106
    Abstract: A method, apparatus, and system for providing layer concurrency connecting two or more master Intellectual Property cores to a Network on a Chip (NoC) for an integrated circuit is provided. An embodiment includes two masters connected using a common tightly coupled protocol to a first interface of an NoC. A protocol conversion unit can be coupled between the two or more masters and the NoC to convert a request in the tightly coupled protocol to a decoupled protocol that decouples request phasing from response phasing and then passes the request in the decoupled protocol format onto the NoC. The system also provides for arbitration amongst the two or more masters. Requests from the masters are still in the common tightly coupled protocol and are translated by the protocol conversion unit into a request in a decoupled protocol to enable out of order return of responses.
    Type: Application
    Filed: November 2, 2010
    Publication date: May 3, 2012
    Applicant: SONICS, INC.
    Inventors: BENOIT DE LESCURE, KRISHNAN SRINIVASAN
  • Publication number: 20120036509
    Abstract: A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 9, 2012
    Applicant: SONICS, INC
    Inventors: KRISHNAN SRINIVASAN, RUBEN KHAZHAKYAN, HARUTYUN ASLANYAN, DREW E. WINGARD, CHIEN-CHUN CHOU
  • Patent number: 8108648
    Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler couples to a target memory core that includes a bank of memories. The memory scheduler contains two or more configurable address tiling functions to transform an incoming address of data requested in a request to the target memory core to determine what physical addresses in the bank of memories will service the first request. The two or more configurable address tiling functions are programmable by a user to create two or more distinctly different memory regions in the target memory core. Each memory region has its own distinct tiling function based on configuration parameters 1) selected by the user and 2) stored in tiling registers in the memory scheduler. The multiple tiling functions are configured to operate concurrently in the integrated circuit.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: January 31, 2012
    Assignee: Sonics, Inc.
    Inventors: Krishnan Srinivasan, Drew E. Wingard, Vida Vakilotojar, Chien-Chun Chou
  • Patent number: 8073820
    Abstract: Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design having one or more bus interconnects. A relational database may have defined tables designed for interconnect analysis of transactions occurring between initiator intellectual property (IP) cores and target IP cores of the electronic design. A query tool may be configured to format input data to be stored in the defined tables, and have application programming interfaces to retrieve data from the defined tables based on performing a query. The query tool executes an algorithm based on the query to provide the interconnect analysis.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: December 6, 2011
    Assignee: Sonics, Inc.
    Inventors: Krishnan Srinivasan, Chien-Chun Chou, Pascal Chauvet
  • Publication number: 20110265050
    Abstract: A high level intermediate representation of a binary is generated. Circuit nodes from the high level intermediate representation are built, wherein a circuit node represents an operation in the high level intermediate representation. The circuit nodes are connecting using a flow analysis of the binary to build a circuit that represents the binary.
    Type: Application
    Filed: July 4, 2011
    Publication date: October 27, 2011
    Applicant: Microsoft Corporation
    Inventors: Hari Krishnan Srinivasan, Perraju Bendapudi
  • Patent number: 7996798
    Abstract: A high level intermediate representation of a binary is generated. Circuit nodes from the high level intermediate representation are built, wherein a circuit node represents an operation in the high level intermediate representation. The circuit nodes are connecting using a flow analysis of the binary to build a circuit that represents the binary.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: August 9, 2011
    Assignee: Microsoft Corporation
    Inventors: Hari Krishnan Srinivasan, Perraju Bendapudi
  • Patent number: 7945631
    Abstract: The present invention extends to methods, systems, and computer program products for maintaining message state at a cursor. A message consumer requests messages from a cursor. The cursor can maintain state information for the message consumers separately from a message log that stores messages. Any of a variety of message delivery assurances can be used when delivering a message to a message consumer.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: May 17, 2011
    Assignee: Microsoft Corporation
    Inventors: Gueorgui Chkodrov, Richard D. Hill, Craig A. Critchley, Krishnan Srinivasan, Tihomir Tarnavski, Mitchell G. Morris, Pramod Gurunath
  • Patent number: 7945819
    Abstract: The present invention extends to methods, systems, and computer program products for maintaining message state at a message log. Messages are accumulated at a message log in accordance with a message retention policy. Any of a variety of message capture assurances can be used when capturing a message from a message producer within a message log. A message becomes visible to message consumers after the outcome of writing the message is known (either failure or success). Messages are requested using (e.g., monotonically increasing) sequence numbers. Messages are also dropped from the message log in accordance with the message retention policy.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: May 17, 2011
    Assignee: Microsoft Corporation
    Inventors: Gueorgui Chkodrov, Richard D. Hill, Craig A. Critchley, Krishnan Srinivasan, Tihomir Tarnavski, Mitchell G. Morris, Pramod Gurunath