Abstract: Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICB) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICB circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1:1 fashion and in a compressed to map packetized memory-mapped traffic to the C2C interconnections in a less-than 1:1 fashion.

Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

Abstract: An integrated circuit (IC) includes a video buffer memory and display driver circuitry. The video buffer memory includes a buffer memory map. The video buffer memory stores one or more raster lines of video data organized as tiled lines. Each of the tiled lines including two quartiles. The display driver circuitry is coupled to the video buffer memory. The display driver circuitry writes data associated with a portion of a first data line to a first one of the two quartiles of a first one of the tiled lines, and updates the buffer memory map. Further, the display driver determines a full display line being present within the video buffer memory based on the buffer memory map. The display driver further outputs the full display line to a display device.

Abstract: An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.

Abstract: Transmitter circuitry includes inversion circuitry, first transform circuitry, and selection circuitry. The inversion circuitry generates a first transformed data word by inverting one or more of a plurality of bits of a first data word. The first transform circuitry generates a second transformed data word by performing a first invertible operation on the first data word and a second data word. The selection circuitry selects one of the first data word, the first transformed data word, and the second transformed data word based on a first number of bit inversions between the first data word and the second data word, a second number of bit inversions between the first transformed data word and the second data word, and a third number of bit inversions between the second transformed data word and the second data word. The selection circuitry further outputs the selected data word.

Abstract: Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.

Abstract: Embodiments herein describe offloading encryption activities to a network interface controller/card (NIC) (e.g., a SmartNIC) which frees up server compute resources to focus on executing customer applications. In one embodiment, the smart NIC includes a system on a chip (SoC) implemented on an integrated circuit (IC) that includes an embedded processor. Instead of executing a transport layer security (TLS) stack entirely in the embedded processor, the embodiments herein offload certain TLS tasks to a Public Key Infrastructure (PKI) accelerator such as generating public-private key pairs.

Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

Abstract: Synthetic molecular tags are placed on an item at various points in a supply chain to create a molecular record of movement through the supply chain. Associations between each unique synthetic molecular tag and individual locations in the supply chain are stored in an electronic record which may be maintained in the cloud. The synthetic molecular tags are collected from the item and sequenced to determine movement of the item through the supply chain by reference to the electronic record. The synthetic molecular tags can be used for identifying recalled items based on locations in the supply chain associated with a recall. The synthetic molecular tags may be polynucleotides such as deoxyribose nucleic acid (DNA). The item may be any type of item including food.

Abstract: Embodiments herein describe on-demand packetization where data that is too large to be converted directly into data words (DWs) for a chip-to-chip (C2C) interface are packetized instead. When identifying a protocol word that is larger than the DW of the C2C interface, a protocol layer can perform packetization where a plurality of protocol words are packetized and sent as a transfer. In one embodiment, the protocol layer removes some or all of the control data or signals in the protocol words so that the protocol words no longer exceed the size of the DW. These shortened protocol words can then be mapped to DWs and transmitted as separate packets on the C2C. The protocol layer can then collect the portion of the control data that was removed from the protocol words and transmit this data as a separate packet on the C2C interface.

Abstract: Transmitter circuitry includes inversion circuitry, first transform circuitry, and selection circuitry. The inversion circuitry generates a first transformed data word by inverting one or more of a plurality of bits of a first data word. The first transform circuitry generates a second transformed data word by performing a first invertible operation on the first data word and a second data word. The selection circuitry selects one of the first data word, the first transformed data word, and the second transformed data word based on a first number of bit inversions between the first data word and the second data word, a second number of bit inversions between the first transformed data word and the second data word, and a third number of bit inversions between the second transformed data word and the second data word. The selection circuitry further outputs the selected data word.

Abstract: Embodiments herein describe on-demand packetization where data that is too large to be converted directly into data words (DWs) for a chip-to-chip (C2C) interface are packetized instead. When identifying a protocol word that is larger than the DW of the C2C interface, a protocol layer can perform packetization where a plurality of protocol words are packetized and sent as a transfer. In one embodiment, the protocol layer removes some or all of the control data or signals in the protocol words so that the protocol words no longer exceed the size of the DW. These shortened protocol words can then be mapped to DWs and transmitted as separate packets on the C2C. The protocol layer can then collect the portion of the control data that was removed from the protocol words and transmit this data as a separate packet on the C2C interface.

Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

Abstract: Examples are disclosed that relate to an energy data platform. One example provides a method comprising receiving a first energy data set having a first data format, and a second energy data set having a second data format, and ingesting the first energy data set and the second energy data set by automatically converting one or more of the first energy data set and the second energy data set into a standard data format. The method further comprises receiving a request from a first application to provide the first energy data set in the first data format, and in response, providing the first energy data set in the first data format, and receiving a request from a second application to provide the first energy data set in the standard data format, and in response, providing the first energy data set in the standard data format.

Abstract: A computing device including a processor is provided. For one or more emissions factors, the processor may be configured to receive respective emissions factor data including sensor data received from one or more sensors and user-specified data received at a user interface. The processor may be further configured to receive a plurality of virtual sensor models. Each virtual sensor model may include one or more respective virtual sensor model parameters. At least in part by applying the virtual sensor models to the emissions factor data, the processor may be further configured to compute a plurality of virtual sensor readouts. The processor may be further configured to generate a greenhouse gas emissions estimate from the virtual sensor readouts. The processor may be further configured to convey an indication of the greenhouse gas emissions estimate to the user interface for output on one or more output devices.

Abstract: One example provides a computing system configured to implement a greenhouse gas (GHG) tracking and auditing platform for tracking GHG emissions associated with a plurality of GHG entities, each GHG entity representing one or more of a GHG source and a GHG sink. The computing system comprises a logic subsystem and a data-holding subsystem comprising computer-readable instructions. The instructions are executable to receive sensor data over time from each sensor of one or more sensors, each sensor configured to sense data related to GHG emissions. The instructions are further executable to, for each time interval of a plurality of time intervals, determine a GHG emission amount based at least in part on the sensor data and store GHG emission data. The instructions are further executable to receive a request for a set of GHG emission data and in response to the request, output the set of GHG emission data.

Abstract: A platform for providing projections, predictions, and recommendations for casino and gaming environments. The platform leverages machine learning and cognitive computing. Through a natural language interface, the platform presents this information in a way which is natural and timely for casino operational executives to understand and act upon. The platform can optimize gaming machine performance casino floor performance based on various metrics that are predicted by the platform.

Abstract: A system and method for automated resolution of events in a computing environment is provided. Problem types are identified from the events which are associated with configuration items (CIs) at issue. Further, domains of the CIs at issue are identified. Domains represent types of the CIs at issue. Existence of diagnosis and resolution sequences is checked which is based on identified problem types and domain associated with the CI types. Thereafter, diagnosis and resolution sequences are fetched, where sequences fetched at a first instance are at least in part updated with one or more new sequences. Fetched sequences are executed iteratively such that a next step of the executed diagnosis and resolution sequence is based on an output of a first step of the executed diagnosis and resolution sequence.

Abstract: A scalable data feed system is disclosed. The data feed system may be offered as a cloud service that can serve many enterprises or tenants that require data to be pulled from information sources such as FTP, POP3, databases, line of business systems, a topic subscription, or an RSS feed, and pushed the data to information sinks, such as SMTP, email, FTP, mobile phones, and other devices and services. A pull agent pumps data from pull sources and pushes the data out to push agent counterparts. The push agent transforms and sends the data in messages to push sink, such as FTP, SMTP, or a mobile device. Both the pull agent and the push agent services are implemented as replicated services over a structured overlay network for high availability that can serve multiple requests to pump out data from multiple pull sources and push the data to multiple information sinks.

Abstract: Systems and methods may support inter-artifact generation for interfaces of a modeled system. In some implementations, a system may include an inter-artifact model repository that stores system model data of a model system as well as an artifact extraction engine configured to extract system model data from a system artifact that represents the modeled system and store the extracted system model data in the inter-artifact model repository. The system may further include an artifact generation engine configured to generate a different system artifact that represents the modeled system using at least some of the extracted system model data extracted from the system artifact.