Abstract: A folding circuit is provided for outputting a periodic function representative of an analog input signal. The circuit includes at least two preamplifiers and a third differential amplifier circuit coupled to the preamplifier circuits for providing a bias current such that the flow of current is regulated through one of the preamplifier circuits at any given time, thereby providing a periodic function representative of an analog input signal.

Abstract: An image sensor (10) which can be fabricated using conventional CMOS processes uses a comparator circuit (18) at each pixel (14) having a first input coupled to a photodetector (16) and a second input coupled to a ramp signal generator (30, 32). The ramp signal generator (30, 32) is comprised of a counter (32) and a D/A conversion circuit (30) with the analog output of the D/A conversion circuit (30) forming an analog ramp input to the comparator circuit (18). A counter circuit (32) can be used to drive the digital side of the D/A conversion circuit (30) and configured to count from 0 to 2n−1 to 0, N being the resolution of the photodetector (16). The output of the D/A conversion circuit (30) causes comparator circuit (18) to flip when the ramp signal is equal to the value of the output from the photodetector (16). The comparator circuit (18), in turn, drives a load signal to a register (38) which stores the counter values 32 from pixel (14) at the instant the comparator 18 flips.

Abstract: An addition is made to the prior art amplifier of additional transistor (M9) controlled by the input voltage, Vin, in series with the second stage (M5, M6) and a capacitor level shifter (C1) between the output of the first stage (junction of M2 and M3) of the amplifier and the gate terminal of the source follower transistor M7. This capacitor C1 is charged such that the signal between the first stage and the source follower stage sees an upward dc voltage shift, thus maintaining the quiescent gate voltage for the source follower transistor M7 close to or even higher than the supply voltage while maintaining the quiescent voltage at the output of the first stage (junction of M1 and M2) sufficiently low for transistors M2 and M3 to operate in saturation regions.

Abstract: An A/D converter which includes a sample-and-hold circuit having an input and an output, a zero-crossing detector having an input coupled to the output of the sample-and-hold circuit and having an output indicative of a change in polarity of an input signal thereto and a polarity reverser having an input coupled to the output of the sample-and-hold circuit, a control terminal coupled to and under control of the output of the zero-crossing detector and an output terminal. A bank of comparators, preferably in a first and second array, each have inputs respectively coupled to the output of the polarity reverser, each comparator having an output. An encoder preferably having first and second portions is coupled to the output of the comparator, the first array preferably coupled to the first encoder portion and the second array preferably coupled to the second encoder portion, the encoder having an output.

Abstract: A digital self calibration scheme for pipelined AD converters. The scheme can correct for capacitor mismatch, capacitor non-linearity, amplifier gain and amplifier non-linearity.

Abstract: A digital self calibration scheme for pipelined AD converters. The scheme can correct for capacitor mismatch, capacitor non-linearity, amplifier gain and amplifier non-linearity.

Abstract: A high speed sigma-delta A/D converter for a sequence of analog samples xn (n=0,1,2, . . . N−1) has an input, a plurality N−1 of phase clocks &PHgr;n, a plurality of sample-hold circuits 40n, a plurality N−1 of circuit stages, and a D/A converter. The input receives the analog samples xn. The sample-hold circuits 40n are coupled to the input and each responds to a respective phase clock &PHgr;n to sample and hold a corresponding analog sample Xn. Each circuit stage n has a summer 42n and a quantizer 44n. The summer has (i) a data input receiving a data signal (xn) from a corresponding sample-hold circuit 40n, (ii) a prior sum signal (wn−1) input, and (iii) a prior quantized signal (yn−1) negative input. The summer 42n produces a sum signal (wn=xn+wn−−Yn−1) at a summer output. The quantizer 44n is coupled to the summer's output for quantizing the sum signal wn into a quantized sum signal yn.

Abstract: A method and apparatus for adjusting the output common-mode of a differential amplifier is disclosed. This is accomplished by reducing the supply voltage to the differential amplifier during the auto-zero mode and returning the supply voltage to the original level during the amplification mode.

Abstract: A digital-to-analog converter (DAC) and a method of converting digital numbers to analog equivalents. In one embodiment, the DAC includes: (1) a data decoder that receives a digital number and an input clock signal and develops therefrom SIGN and M control signals and complementary .phi..sub.1 and .phi..sub.2 clock signals and (2) a conversion circuit, coupled to the data decoder and including first and second operational amplifiers (op amps), a switching circuit and sampling and integrating capacitors, the switching circuit coupling positive and negative reference voltages to the sampling capacitors as a function of states of the SIGN and M control signals and adjusting feedback loops associated with the first and second op amps as a function of states of the .phi..sub.1 and .phi..sub.2 clock signals, the first and second op amps generating a voltage difference at outputs thereof representing an analog equivalent of the digital number.

Abstract: A slicer circuit receives a binary signal to be sliced at the midpoint of its amplitude with the portions of the sliced signal above the slicing level corresponding to a binary 1 and the portions below corresponding to a binary 0. The slicer has a fixed threshold level for slicing and a variable offset voltage is combined with the voltage level of the received binary signal to maintain the mid-point of the binary signal applied to the slicer at the slicer fixed threshold slicing level, which preferably is at a zero voltage level.

Abstract: An apparatus for detecting when a dynamic signal is stable. The apparatus is couplable to a first charge pump connected to receive the dynamic signal and generate a first signal as a function of the dynamic signal. The first charge pump has a predetermined capacitance and current.

Abstract: In an amplifier stage a first FET receives the input signal at its gate electrode. The drain of the first FET is connected to the drain of a second FET, and both drains are connected to the same drain voltage supply. The amplifier stage output is from the drain of the second FET. A third FET has its drain connected to the drain voltage supply and its source connected to the reference voltage supply. The physical characteristics of the third transistor are selected to produce a voltage of a fixed value that is applied as a bias to the source of the second transistor to compensate for an offset of the amplifier stage input signal voltage. A fourth FET has its drain connected to the drain voltage supply and its source connected to the drain of the third FET. The drain of the fourth FET is connected to the gate of the second FET. The physical characteristics of the fourth FET and the current flowing through it determine the gain of the amplifier stage. The third and fourth FETs are not in the signal path.

Abstract: A high Q bandpass filter (102) is tuned by applying a transient (204) to the filter to cause it to ring. The ringing of the filter produces an output damped oscillatory waveform (206) whose zero crossings (208) are converted to a pulse train (210) and counted in a digital counter (112) to a predetermined number n. The output (214) of the counter is compared to an accurate timing signal (216) which has a time duration equal to the time of n pulses when the filter is accurately tuned. The output of the comparator (118) is applied to an integrator (122) to generate a control signal V.sub.c to tune the filter. The high frequency tuning problem is thus converted to a low frequency, time domain problem which is readily implemented.

Abstract: A bootstrap clock generator powered by a variable DC power supply voltage signal generates an approximate boost voltage signal depending on the DC power supply voltage signal level. The clock generator comprises a capacitor having a first and a second terminal and a first switching circuit coupled to the first terminal so as to couple the variable voltage supply signal to the first terminal. A second switching circuit is coupled to the second terminal so as to couple a variable reference voltage signal to the second terminal. A third switching circuit is coupled to the second terminal so as to connect a substantially fixed reference voltage signal to the second terminal. A first and a second control signal activates the switching circuits, such that the first control signal activates the first and second switching circuits, and the second control signal activates the third switching circuit.

Abstract: The first amplifier stage in the A/D converter receives an analog input signal and generates an analog residue signal and a digital output signal. Any other amplifier stage in the A/D converter receives the analog residue signal and the digital output signal from the previous amplifier stage, and generates another analog residue signal and another digital output signal. The comparator stage receives the analog residue signal and the digital output signal from the last amplifier stage, and generates one or more additional digital output signals. The digital output signals from all of the stages are used to generate the digitized equivalent of the original analog input signal. Because the comparator stage can be designed without an amplifier, the total number of amplifiers required to implement the A/D converter is reduced, as compared to prior art techniques.

Abstract: A receiver for decoding passband signal pulses transmitted in accordance with a M-ARY phase shift keying modulation scheme, comprises a multiphase sampler for sampling received passband signal pulses in the passband frequency range so as to generate a plurality of digital words corresponding to the sampled passband signal pulses, such that each digital word represents the phase of each sampled passband signal pulse. A phase reference register or other storage device is coupled to the multiphase sampler for storing one of the digital words as a phase reference such that other digital words generated by the multiphase sampler are compared with the digital word corresponding to the phase reference for decoding the passband signal pulses.

Abstract: A differential amplifier has (at least) four input-stage transistors that are switchably coupled to the inverting and noninverting input terminals and to the output terminal(s). In one embodiment, two of the transistors are permanently coupled between the input and output terminals, while the other two transistors are switchably coupled the input and output terminals, such that, during two-phased operations, each of the switchably coupled transistors is alternately connected in parallel to a different one of the two permanently coupled transistors. In this way, any charge (due to input capacitance) in one input-stage transistor from the previous clock phase will tend to negate similar charge in another input-stage transistor at the start of each clock phase. Such an amplifier can be efficiently used in time-sharing applications.

Abstract: A phase detector for a phase-locked loop ("PLL") circuit under control of a local oscillating clock ("LOSC") signal and a method of operation thereof.

Abstract: An adaptive equalizer capable of providing compensation for a wide range of cables having different cable characteristics and different cable lengths. The adaptive equalizer comprises a programmable gain amplifier capable of providing a variable amplification factor in response to a feedback control signal. The gain amplifier is configured to receive pulse signals transmitted over a communication channel. A peak detecting equalizer is coupled to the gain amplifier so as to receive its output signals. A pulse shape detector is adapted to receive pulse signals provided by the peak detecting equalizer, and generate a first indication signal indicating over-equalization and a second indication signal indicating under-equalization. A gain control circuit receives the first and second indication signals to provide the feedback control signal to the programmable gain amplifier so as to vary its amplification factor.

Abstract: A voltage-to-current converter configured to operate over substantially the entire range of a power supply voltage signal that is employed to drive the voltage-to-current converter. A closed-loop voltage-to-current converter is configured to provide a first output current signal substantially linearly responsive to a predetermined range of an input voltage signal having values between the low voltage level of the power supply and a predetermined reference voltage signal. An open loop voltage-to-current converter is coupled to the closed-loop voltage-to-current converter. It is configured to provide a second output current signal, substantially linearly responsive to a predetermined range of input voltage signals, having values ranging between the reference voltage level and the high voltage level of the power supply. The first and second output currents are combined to provide the output current signal of the voltage-to-current converter.