Abstract: The disclosure describes a method of monitoring the dynamic power consumption of ReRAM crossbars and determines the occurrence of faults when a changepoint is detected in the monitored power-consumption time series. Statistical features are computed before and after the changepoint and train a predictive model using machine-learning techniques. In this way, the computationally expensive fault localization and error-recovery steps are carried out only when a high fault rate is estimated. With the proposed fault-detection method and the predictive model, the test time is significantly reduced while high classification accuracy for well-known AI/ML datasets using a ReRAM-based computing system (RCS) can still be ensured.

Abstract: An integrated circuit (IC) protection circuit can include a reconfigurable block that receives a seed value from a tamper-proof memory and generates a dynamic key; an authentication block that receives the dynamic key from the reconfigurable block and taint bits from a scan chain to generate an authentication signature; and an encryptor that encrypts a test pattern response on the scan chain if a mismatch is found between the authentication signature and a test pattern embedded signature.

Abstract: A method for identifying observation points for integrated circuit (IC) testing includes receiving a netlist for an IC that includes a first subcircuit and a second subcircuit; determining, from the netlist, one or more observation points, each determined observation point corresponding to an output node which provides observability, into at least the first subcircuit, of an effective number of gates above a specified threshold; and inserting a design for test element into a layout file of the IC at each determined observation point. Observation points can be determined by transforming the netlist into a node graph; assigning a same initial value to a value field of each node; and propagating values in the value fields of the nodes until all nodes with a succeeding edge have a value of zero in their value fields.

Abstract: An integrated circuit (IC) protection circuit for an IC includes a controller with a barrier finite state machine (FSM) having a key sequence input that unlocks the controller; and a signal scrambler coupled to receive at least two initialization inputs and a primary input path and output a signal to the IC, wherein at least one initialization input of the at least two initialization inputs is based on an output of the barrier FSM. The IC protection circuit can further include a dynamic authentication circuit coupled to receive the output of the barrier finite state machine and output a signal to the signal scrambler for one of the at least two initialization inputs. The dynamic authentication circuit can be formed of a dynamic sequence generator and a dynamic sequence authenticator, each formed of one or more reconfigurable linear feedback shift registers, and a comparator.

Abstract: A method of fault criticality assessment using neural twins includes converting a netlist into a neural twin by replacing each circuit element of the netlist with a neural-network-readable cell equivalent; and replacing each wire with a neural connection. Bias value adders are inserted at locations in the neural twin; and these bias value adders are used to apply a bias that represents a perturbation in the signal propagated by that connection. For each perturbed bias at a corresponding site selected to be perturbed, a loss value is calculated for the neural twin; and the site is classified, using a neural-twin-trained classifier, as critical or benign based on that loss value.

Abstract: Variation-aware delay fault testing suitable for carbon nanotube field-effect transistor circuits can be accomplished using an electronic design automation tool that performs long path selection by generating random variation scenarios, wherein a random variation scenario (RVS) is an instance of an input netlist where values for a set of process parameters for each gate are chosen from a set of values for each process parameter of the set of process parameters for that gate, the set of values being sampled from a distribution of that particular process parameter for that gate and includes a nominal value for that particular process parameter; calculating a total delay through a path for each RVS; and selecting at least two paths having highest total delays for each fault site under random variations of the RVSs. Delay test patterns can then be generated for the selected paths.

Abstract: A method of fault criticality assessment using a k-tier graph convolution network (GCN) framework, where k?2, includes generating a graph from a netlist of a processing element implementing a target hardware architecture having an applied domain-specific use-case, wherein a logic gate is represented in the graph as a node and a signal path between two logic gates is represented in the netlist-graph as an edge; evaluating functional criticality of unlabeled nodes of the graph using a trained first GCN, and evaluating nodes classified as benign by the trained first GCN using a trained second GCN to identify misclassified nodes.

Abstract: A system for evaluating fault criticality using machine learning includes a first machine learning module that is trained on a subset of a circuit and used for evaluating whether a node in a netlist of the entire circuit is a critical node, and a second machine learning module specialized to minimize classification errors in nodes predicted as benign. A generative adversarial network can be used to generate synthetic test escape data to supplement data used to train the second machine learning module.

Abstract: The disclosure describes a method of monitoring the dynamic power consumption of ReRAM crossbars and determines the occurrence of faults when a changepoint is detected in the monitored power-consumption time series. Statistical features are computed before and after the changepoint and train a predictive model using machine-learning techniques. In this way, the computationally expensive fault localization and error-recovery steps are carried out only when a high fault rate is estimated. With the proposed fault-detection method and the predictive model, the test time is significantly reduced while high classification accuracy for well-known AI/ML datasets using a ReRAM-based computing system (RCS) can still be ensured.

Abstract: The disclosure provides misclassification-driven training (MDT) that efficiently identifies critical faults in neuromorphic hardware, such as a memristor crossbar. MDT advantageously identifies whether a hardware fault is a critical fault and can be used to limit fault recovery when a hardware fault is not a critical fault. By applying fault-tolerant techniques directed to critical faults, such as only for critical faults, processing overhead of a neural network can be reduced. In one aspect, the disclosure provides a method of identifying critical faults in neuromorphic hardware of a neural network. In one example the method of identifying includes: (1) determining a significant parameter of a trained neural network that impacts classification of a sample of a dataset, (2) obtaining a location of the significant parameter in the neuromorphic hardware, and (3) identifying the location as a critical fault of the neuromorphic hardware.

Abstract: Variation-aware delay fault testing suitable for carbon nanotube field-effect transistor circuits can be accomplished using an electronic design automation tool that performs long path selection by generating random variation scenarios, wherein a random variation scenario (RVS) is an instance of an input netlist where values for a set of process parameters for each gate are chosen from a set of values for each process parameter of the set of process parameters for that gate, the set of values being sampled from a distribution of that particular process parameter for that gate and includes a nominal value for that particular process parameter; calculating a total delay through a path for each RVS; and selecting at least two paths having highest total delays for each fault site under random variations of the RVSs. Delay test patterns can then be generated for the selected paths.

Abstract: A method for identifying observation points for integrated circuit (IC) testing includes receiving a netlist for an IC that includes a first subcircuit and a second subcircuit; determining, from the netlist, one or more observation points, each determined observation point corresponding to an output node which provides observability, into at least the first subcircuit, of an effective number of gates above a specified threshold; and inserting a design for test element into a layout file of the IC at each determined observation point. Observation points can be determined by transforming the netlist into a node graph; assigning a same initial value to a value field of each node; and propagating values in the value fields of the nodes until all nodes with a succeeding edge have a value of zero in their value fields.

Abstract: Embedded processor-based self-test and diagnosis using the compressed test data is described for ICs having on-chip memory. Techniques for compressing the test data before the compressed test data is transferred to a device under test (DUT) are also described. A modified LZ77 algorithm can be used to compress strings of test data in which don't care bits are handled by assigning a value to the don't care bits according to a longest match in the window as the data is being encoded. The compressed test data can be decompressed at the DUT using a software program transferred by the automated test equipment (ATE) to the DUT with the compressed test data. Decompression and diagnostics can be carried out at the DUT using an embedded processor and the on-chip memory. Results from the diagnostics can be read by the ATE.

Abstract: Multi-layer integrated circuits having isolation cells for layer testing and related methods are disclosed. According to an aspect, an integrated circuit includes multiple isolation cells. Example isolation cells include, but are not limited to, electronic fuses and tri-state flip-flops. The integrated circuit also includes a first layer having first and second sets of electronic components, the first set of electronic components being operatively connected to the second set of electronic components via the isolation cells. Further, the integrated circuit includes multiple transmission gates associated with the isolation cells. The integrated circuit also includes a second layer having electrical circuitry operatively connected to the electronic components of the first layer. The electrical circuitry is configured to apply test patterns to the electronic components of the first layer.

Abstract: Embedded processor-based self-test and diagnosis using the compressed test data is described for ICs having on-chip memory. Techniques for compressing the test data before the compressed test data is transferred to a device under test (DUT) are also described. A modified LZ77 algorithm can be used to compress strings of test data in which don't care bits are handled by assigning a value to the don't care bits according to a longest match in the window as the data is being encoded. The compressed test data can be decompressed at the DUT using a software program transferred by the automated test equipment (ATE) to the DUT with the compressed test data. Decompression and diagnostics can be carried out at the DUT using an embedded processor and the on-chip memory. Results from the diagnostics can be read by the ATE.

Abstract: Monolithic three-dimensional integration can achieve higher device density compared to 3D integration using through-silicon vias. A test solution for M3D integrated circuits (ICs) is based on dedicated test layers inserted between functional layers. A structure includes a first functional layer having first functional components of the IC with first test scan chains and a second functional layer having second functional components of the IC with second test scan chains. A dedicated test layer is located between the first functional layer and the second functional layer. The test layer includes an interface register controlling signals from a testing module to one of the first test scan chains and the second test scan chains, and an instruction register connected to the interface register. The instruction register processes testing instructions from the testing module. Inter-layer vias connect the first functional components, the second functional components, and the testing module through the test layer.

Abstract: A post-fabrication debug and on-line error checking framework for 2D- and 3D-ICs with integrated memories is described. A design-for-debug (DfD) architecture can include, for an IC with on-chip memory, a debug module connected to a functional bus of the IC. The debug module receives trace data for an interval, generates compact signatures based on the received data, and compares these signatures to expected signatures. Intervals containing erroneous trace data can be identified by the debug module and stored in on-chip memory. A single iteration of signal tracing for debug testing between automated test equipment and the IC is possible.

Abstract: A design for test (DfT) architecture is provided that enables pre-bond parametric testing of through-silicon vias (TSVs). A grouping of N number of input/output (I/O) segments are configured to receive a test signal in a feedback loop, where each I/O segment includes one or more buffers (or inverters) and a TSV connected at one end to the one or more buffers. The TSV acts as a shunt-connected capacitor—when defect free—and includes a load resistance when the TSV contains a defect. Each I/O segment can also include one or two multiplexers to control whether the I/O segment receives a test or functional signal and, optionally, whether the I/O segment is bypassed or included in the ring oscillator. The varying loads caused by the defects cause variations in the delay across the buffers (or inverters) of an I/O segment that can be detected in the output signal.

Abstract: Multi-layer integrated circuits having isolation cells for layer testing and related methods are disclosed. According to an aspect, an integrated circuit includes multiple isolation cells. Example isolation cells include, but are not limited to, electronic fuses and tri-state flip-flops. The integrated circuit also includes a first layer having first and second sets of electronic components, the first set of electronic components being operatively connected to the second set of electronic components via the isolation cells. Further, the integrated circuit includes multiple transmission gates associated with the isolation cells. The integrated circuit also includes a second layer having electrical circuitry operatively connected to the electronic components of the first layer. The electrical circuitry is configured to apply test patterns to the electronic components of the first layer.

Abstract: Multi-layer integrated circuits having isolation cells for layer testing and related methods are disclosed. According to an aspect, an integrated circuit includes first and second layers that each have one or more electronic components. One or more electronic components of each layer can be electrically connected by a first via and a second via. The integrated circuit also includes an isolation cell operatively connected between the first via and the second via. The isolation cell is configured to controllably break electrical connection between the first via and the second via subsequent to testing of the at least one electronic component of the second layer. Example isolation cells include, but are not limited to, electronic fuses and tri-state flip-flops.