Abstract: A design for test (DfT) architecture is provided that enables pre-bond parametric testing of through-silicon vias (TSVs). A grouping of N number of input/output (I/O) segments are configured to receive a test signal in a feedback loop, where each I/O segment includes one or more buffers (or inverters) and a TSV connected at one end to the one or more buffers. The TSV acts as a shunt-connected capacitor—when defect free—and includes a load resistance when the TSV contains a defect. Each I/O segment can also include one or two multiplexers to control whether the I/O segment receives a test or functional signal and, optionally, whether the I/O segment is bypassed or included in the ring oscillator. The varying loads caused by the defects cause variations in the delay across the buffers (or inverters) of an I/O segment that can be detected in the output signal.

Abstract: A test architecture for 3D ICs is provided in which Through-Silicon-Vias and die logic can be tested pre-bonding dies in the stack for the 3D ICs. Post-bond scan test architecture is reconfigured to be accessed during pre-bond testing through using stratigically placed MUXs and TSVs. By connecting post-bond architecture including scan flops and boundary registers to gated scan flops used in TSV testing, an internal chain of scan flops such as typically used in post-bond testing can be selectively connected to gated scan flops connected to one end of each TSV for pre-bond testing of the internal logic through the TSVs.

Abstract: On-chip test architecture and design-for-testability methods for pre-bond testing of TSVs are provided. In accordance with certain embodiments of the invention, a die level wrapper is provided including gated scan flops connected to one end of each TSV. The gated scan flops include a scan flop structure and a gated output. The gated output is controlled by a signal to cause the output of the gated scan flop to either be in a “floated state” or take the value stored in the flip-flop portion of the gated scan flop. The gated output of the gated scan flop can be used to enable resistance and capacitance measurements of pre-bonded TSVs.

Abstract: Validating feasibility of proposed contract provisions includes obtaining a job request with a proposed contract provision at a validation engine, obtaining at the validation engine status information from a production monitoring engine that monitors production resources for completing the job request, and determining with the validation engine whether the proposed contract provision is feasible for executing the job request with the production resources.

Abstract: A test architecture for 3D ICs is provided in which Through-Silicon-Vias and die logic can be tested pre-bonding dies in the stack for the 3D ICs. Post-bond scan test architecture is reconfigured to be accessed during pre-bond testing through using stratigically placed MUXs and TSVs. By connecting post-bond architecture including scan flops and boundary registers to gated scan flops used in TSV testing, an internal chain of scan flops such as typically used in post-bond testing can be selectively connected to gated scan flops connected to one end of each TSV for pre-bond testing of the internal logic through the TSVs.

Abstract: Systems and methods are provided for producing fluids with desired concentration factors. According to one embodiment, a sequence of mix steps comprises mixing a resultant solution of a preceding mix step with one of the input solutions of the preceding mix step depending on a concentration factor of the resultant solution. If the concentration factor of the resultant solution is higher than the target concentration factor, then the resultant solution is mixed with the input solution having the lower concentration factor. If the concentration factor of the resultant solution is lower than the target concentration factor, then the resultant solution is mixed with the input solution having the higher concentration factor.

Abstract: Systems and methods are provided for producing fluids with desired concentration factors. According to one embodiment, an arrangement of digital microfluidic (DMF) based electrode platforms are provided. The arrangement may be configured to carry out a sequence of mix steps that may demand storage of resultant fluid mixtures produced in intermediate mix steps. Such sequences of mix steps may be desirable as a result of the decreased demand for initial fluid samples, and reduced wastage.

Abstract: Systems and methods are provided for producing fluids with desired concentration factors from the given supply of any two concentration factors, one greater than the target CF and one less than the target CF, of the same fluid. According to one embodiment, a method is provided that stores intermediate waste droplets from a sequence of mix and split steps and repeats certain steps of the sequence using the stored intermediate waste droplets. Such a method may produce additional target CF droplets faster than repeating the entire sequence. In another embodiment, a method of volumetric error resilient target CF droplet generation has been described, and includes reusing the stored intermediate waste droplets and involves a collection of capacitive sensing circuits associated with some electrode platforms.

Abstract: Power switching circuits and power management techniques are provided that can reduce static power of ICs, including digital core processors. In one embodiment, the power switching circuit includes a footer (power-gating transistor) between the core and a ground rail and at least two additional power-gating transistors parallel to the footer. The power-gating transistors are controlled by respective control signals to enable selective switching. In a specific embodiment, for each sleep mode, at most, a single one of the transistors is turned on. Multiple sleep modes are accomplished according to the relative sizing of the additional power-gating transistors. A larger of the additional transistors is used to provide a standby mode during short idling times by providing a fast wake-up time and some reduction in static power. For standby modes during longer idling periods, smaller sized transistors are turned on. For longest idling periods, all transistors are turned off.

Abstract: On-chip test architecture and design-for-testability methods for pre-bond testing of TSVs are provided. In accordance with certain embodiments of the invention, a die level wrapper is provided including gated scan flops connected to one end of each TSV. The gated scan flops include a scan flop structure and a gated output. The gated output is controlled by a signal to cause the output of the gated scan flop to either be in a “floated state” or take the value stored in the flip-flop portion of the gated scan flop. The gated output of the gated scan flop can be used to enable resistance and capacitance measurements of pre-bonded TSVs.

Abstract: Power switching circuits and power management techniques are provided that can reduce static power of ICs, including digital core processors. In one embodiment, the power switching circuit includes a footer (power-gating transistor) between the core and a ground rail and at least two additional power-gating transistors parallel to the footer. The power-gating transistors are controlled by respective control signals to enable selective switching. In a specific embodiment, for each sleep mode, at most, a single one of the transistors is turned on. Multiple sleep modes are accomplished according to the relative sizing of the additional power-gating transistors. A larger of the additional transistors is used to provide a standby mode during short idling times by providing a fast wake-up time and some reduction in static power. For standby modes during longer idling periods, smaller sized transistors are turned on. For longest idling periods, all transistors are turned off.

Abstract: A droplet actuator with arrays of electrodes electrically coupled to a number of controllable voltage sources that is less than the number of electrodes. A method of defining partitions for pin layouts in a droplet actuator for a specific assay, the method including: defining droplet traces for the assay; and defining a guard ring along the traces. Other methods, systems, droplet actuators, and algorithms are also provided.

Abstract: An improved network of sensor nodes can self-organize so as to reduce energy consumption and/or improve coverage of a surveillance field. Nodes within the network may be dynamically activated or deactivated so as to lengthen network lifetime and/or enhance sensor coverage of the surveillance field.

Abstract: A circuit with a built-in self test, comprising: a circuit to be tested; a generating circuit coupled to the circuit to be tested, wherein the generating circuit generates (i) a series of input signals to the circuit to be tested and (ii) a series of reference signals; a space compaction circuit coupled to an output of the circuit to be tested, wherein the space compaction circuit uses a categorized response of the circuit to be tested to compact the output of the circuit to be tested by a maximum ratio and produces a series of output signals when the input signals are applied to the circuit to be tested; an analysis circuit coupled to the space compaction circuit and the generating circuit, providing a signal indicative of error in the circuit to be tested when the output signals fail to correspond to the reference signals.