Patents by Inventor Kristof Kuwawi Darmawikarta
Kristof Kuwawi Darmawikarta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11521931Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: GrantFiled: June 16, 2020Date of Patent: December 6, 2022Assignee: Intel CorporationInventors: Jason M. Gamba, Nitin A. Deshpande, Mohit Bhatia, Omkar G. Karhade, Bai Nie, Gang Duan, Kristof Kuwawi Darmawikarta, Wei-Lun Jen
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Publication number: 20220375882Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, including a first conductive pillar, having a first end at the first surface of the magnetic core inductor and an opposing second end at the second surface, at least partially surrounded by a magnetic material that extends at least partially along a thickness of the first conductive pillar from the second end and tapers towards the first end; and a second conductive pillar coupled to the first conductive pillar; and a second die in a second dielectric layer on the first dielectric layer coupled to the second surface of the magnetic core inductor.Type: ApplicationFiled: May 18, 2021Publication date: November 24, 2022Applicant: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Benjamin T. Duong, Srinivas V. Pietambaram, Tarek A. Ibrahim
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Publication number: 20220181166Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Applicant: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
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Patent number: 11309192Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.Type: GrantFiled: June 5, 2018Date of Patent: April 19, 2022Assignee: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
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Patent number: 11244912Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.Type: GrantFiled: March 30, 2017Date of Patent: February 8, 2022Assignee: Intel CorporationInventors: Sai Vadlamani, Aleksandar Aleksov, Rahul Jain, Kyu Oh Lee, Kristof Kuwawi Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati, Telesphor Kamgaing
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Publication number: 20210391266Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: ApplicationFiled: June 16, 2020Publication date: December 16, 2021Applicant: Intel CorporationInventors: Jason M. Gamba, Nitin A. Deshpande, Mohit Bhatia, Omkar G. Karhade, Bai Nie, Gang Duan, Kristof Kuwawi Darmawikarta, Wei-Lun Jen
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Publication number: 20210391264Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: ApplicationFiled: June 16, 2020Publication date: December 16, 2021Applicant: Intel CorporationInventors: Bai Nie, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Haobo Chen, Gang Duan, Jason M. Gamba, Omkar G. Karhade, Nitin A. Deshpande, Tarek A. Ibrahim, Rahul N. Manepalli, Deepak Vasant Kulkarni, Ravindra Vijay Tanikella
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Publication number: 20210358872Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.Type: ApplicationFiled: July 28, 2021Publication date: November 18, 2021Inventors: Srinivas V. PIETAMBARAM, Rahul N. MANEPALLI, Kristof Kuwawi DARMAWIKARTA, Robert Alan MAY, Aleksandar ALEKSOV, Telesphor KAMGAING
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Patent number: 11107781Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.Type: GrantFiled: March 30, 2017Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Srinivas V. Pietambaram, Rahul N. Manepalli, Kristof Kuwawi Darmawikarta, Robert Alan May, Aleksandar Aleksov, Telesphor Kamgaing
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Patent number: 11075130Abstract: Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.Type: GrantFiled: March 30, 2017Date of Patent: July 27, 2021Assignee: Intel CorporationInventors: Lisa Ying Ying Chen, Lauren Ashley Link, Robert Alan May, Amruthavalli Pallavi Alur, Kristof Kuwawi Darmawikarta, Siddharth K. Alur, Sri Ranga Sai Boyapati, Andrew James Brown, Lilia May
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Patent number: 11037802Abstract: Integrated circuit (IC) package substrates having high density interconnects with a sputter seed layer containing a copper alloy, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a package substrate may include a first dielectric layer, a sputter seed layer disposed on the first dielectric layer, wherein the seed layer includes a copper alloy, a patterned conductive layer disposed on the seed layer, and a second dielectric layer over the patterned conductive layer.Type: GrantFiled: December 28, 2016Date of Patent: June 15, 2021Assignee: Intel CorporationInventors: Robert Alan May, Kristof Kuwawi Darmawikarta, Sri Ranga Sai Boyapati, Sandeep Gaan, Srinivas V. Pietambaram
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Publication number: 20210066232Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.Type: ApplicationFiled: November 16, 2020Publication date: March 4, 2021Applicant: Intel CorporationInventors: Robert Alan May, Sri Ranga Sai Boyapati, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Javier Soto Gonzalez, Kwangmo Chris Lim, Aleksandar Aleksov
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Patent number: 10872872Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.Type: GrantFiled: December 30, 2016Date of Patent: December 22, 2020Assignee: Intel CorporationInventors: Robert Alan May, Sri Ranga Sai Boyapati, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Javier Soto Gonzalez, Kwangmo Chris Lim, Aleksandar Aleksov
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Patent number: 10790233Abstract: Disclosed herein are package substrates with integrated components, as well as related apparatuses and methods. For example, in some embodiments, an integrated circuit (IC) package, may include: a substrate having opposing first and second faces, an insulating material disposed between the first and second faces, and a thin film transistor (TFT) disposed between the first and second faces, wherein a conductive portion of the TFT is disposed on a layer of the insulating material, and the conductive portion of the TFT is a gate, source, or drain of the TFT; and a die coupled to the first face of the substrate.Type: GrantFiled: May 25, 2016Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: Robert Alan May, Kristof Kuwawi Darmawikarta, Sri Ranga Sai Boyapati
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Publication number: 20200205279Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.Type: ApplicationFiled: December 21, 2018Publication date: June 25, 2020Applicant: Intel CorporationInventors: Jeremy Ecton, Aleksandar Aleksov, Suddhasattwa Nad, Kristof Kuwawi Darmawikarta, Vahidreza Parichehreh, Veronica Aleman Strong, Xiaoying Guo
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Publication number: 20200168569Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.Type: ApplicationFiled: March 30, 2017Publication date: May 28, 2020Inventors: Sai VADLAMANI, Aleksandar ALEKSOV, Rahul JAIN, Kyu Oh LEE, Kristof Kuwawi DARMAWIKARTA, Robert Alan MAY, Sri Ranga Sai BOYAPATI, Telesphor KAMGAING
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Publication number: 20200091053Abstract: Disclosed herein are integrated circuit (IC) package supports having inductors with magnetic material therein. For example, in some embodiments, an IC package support may include an inductor including a solenoid, a first portion of a magnetic material in an interior of the solenoid, and a second portion of magnetic material outside the interior of the solenoid.Type: ApplicationFiled: September 14, 2018Publication date: March 19, 2020Applicant: Intel CorporationInventors: Sameer Paital, Srinivas V. Pietambaram, Yonggang Li, Kristof Kuwawi Darmawikarta, Gang Duan, Krishna Bharath, Michael James Hill
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Publication number: 20190393172Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.Type: ApplicationFiled: March 30, 2017Publication date: December 26, 2019Inventors: Srinivas V. PIETAMBARAM, Rahul N. MANEPALLI, Kristof Kuwawi DARMAWIKARTA, Robert Alan MAY, Aleksandar ALEKSOV, Telesphor KAMGAING
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Publication number: 20190393109Abstract: Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.Type: ApplicationFiled: March 30, 2017Publication date: December 26, 2019Inventors: Lisa Ying Ying CHEN, Lauren Ashley LINK, Robert Alan MAY, Amruthavalli Pallavi ALUR, Kristof Kuwawi DARMAWIKARTA, Siddharth K. ALUR, Sri Ranga Sai BOYAPATI, Andrew James BROWN, Lilia MAY
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Publication number: 20190371621Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.Type: ApplicationFiled: June 5, 2018Publication date: December 5, 2019Applicant: Intel CorporationInventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov