Abstract: A trusted device, such as a wristwatch 2, is provided with authentication circuitry 26, used to perform an authentication operation to switch the trusted device into an authenticated state. Retention monitoring circuitry 32 monitors the physical possession of the trusted device by the user following the authentication operation and switches the trusted device out of an authenticated state if the trusted device does not remain in the physical possession of the user. While the trusted device remains in the physical possession of the user, communication triggering circuitry 38 is used to detect a request to establish communication with a target device that is one of a plurality of different target devices and communication circuitry 40 is used to communicate with that target device using an authenticated identity of the user.

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract: An envoy device for performing transactions with a further device in proximity to said envoy device, said envoy device comprising a data store, a processor; a first communication device configured to communicate with said further device that is located close enough to said envoy device to establish a first communication link; and at least one further communication device configured to communicate with said further device using at least one further communication link; said envoy device being configured to respond to detecting said further device close enough to said envoy device to establish said first communication link to: establish communication with said further device using said first communication link; receive information from said further device regarding said at least one further communication link that said further device is capable of communicating via and communicating at least one access key for connecting said further device and said first envoy device via said at least one further communication

Abstract: An envoy device for performing transactions with a further device in proximity to the envoy device, the envoy device comprising: a first communication device configured to communicate with the further device that is located within a predetermined distance of the envoy device using a local short range communication link; at least one further communication device configured to communicate with the further device using at least one longer range communication link. The envoy device is configured to respond to detecting the further device within the predetermined distance of the envoy device to: establish communication with the further device using the local short range communication link; receive information from the further device regarding any further communication links that the further device has access to; transmit to the further device information regarding the at least one longer range communication link; and to commence a transaction with the further device using the local short range communication link.

Abstract: An envoy device configured to perform a transaction with a further device. The envoy device comprises: a data store; a processor; communication circuitry for communicating with the further device; and a display. The envoy device is configured to respond to detection of the further device being within a predetermined physical proximity to trigger initiation of a transaction between the devices; and to respond to the transaction completing to display an object related to the transaction that it is determined the user may wish to select to initiate a subsequent action.

Abstract: An envoy device for performing transactions with a further device in proximity to the envoy device, the envoy device comprising: a first communication device configured to communicate with the further device that is located within a predetermined distance of the envoy device using a local short range communication link; at least one further communication device configured to communicate with the further device using at least one longer range communication link. The envoy device is configured to respond to detecting the further device within the predetermined distance of the envoy device to: establish communication with the further device using the local short range communication link; receive information from the further device regarding any further communication links that the further device has access to; transmit to the further device information regarding the at least one longer range communication link; and to commence a transaction with the further device using the local short range communication link.

Abstract: An apparatus, system and method for establishing a transaction between first and second parties including a first signing step in which a transaction message including a request and a transaction identifier is cryptographically signed by the first party to form a first cryptographically signed message. The first signed message is transmitted from the first party to the second party. The second party then cryptographically signs the first message to form a second cryptographically signed message. The second message is also transmitted from one or more of a plurality of parties having the second message to a trusted third party. The trusted third party is able to verify that the second message was cryptographically signed by the second party and can also verify that the first message in the second message was cryptographically signed by the first party.

Abstract: A trusted device, such as a wristwatch 2, is provided with authentication circuitry 26, used to perform an authentication operation to switch the trusted device into an authenticated state. Retention monitoring circuitry 32 monitors the physical possession of the trusted device by the user following the authentication operation and switches the trusted device out of an authenticated state if the trusted device does not remain in the physical possession of the user. While the trusted device remains in the physical possession of the user, communication triggering circuitry 38 is used to detect a request to establish communication with a target device that is one of a plurality of different target devices and communication circuitry 40 is used to communicate with that target device using an authenticated identity of the user.

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract: A data processing system is provided having a processor and analysing circuitry for identifying a SIMD instruction associated with a first SIMD instruction set and replacing it by a functionally-equivalent scalar representation and marking that functionally-equivalent scalar representation. The marked functionally-equivalent scalar representation is dynamically translated using translation circuitry upon execution of the program to generate one or more corresponding translated instructions corresponding to a instruction set architecture different from the first SIMD architecture corresponding to the identified SIMD instruction.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic, a non-delayed signal-capture element, a delayed signal-capture element and a comparator. The non-delayed signal-capture element captures an output from the processing logic at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element also captures a value from the processing logic. An error detection circuit and error correction circuit detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator. The comparator compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: A method of selecting where error detection circuits should be placed within an integrated circuit uses simulation of a reference and test design with errors injected into the test design and then fan out analysis performed upon those injected errors to identify error propagation characteristics. Thus, registers at which propagated errors are highly likely to manifest themselves or which protect key architectural state, or which protect state not otherwise protected can be identified and so an efficient deployment of error detection mechanisms achieved. Within an integrated circuit output signals from inactive circuit elements may be subject to isolation gating in dependence upon a detected current state of the integrated circuit. Thus, inactive circuit elements in which soft errors occur have inappropriate output signals gated from reaching the rest of the integrated circuit and thus reducing erroneous operation.

Abstract: An integrated circuit 78 is formed of multiple layers of circuits 14, 16 superimposed to produce stacks of circuit blocks 2, 4. Stack control circuitry 18, 20 is associated with the input and output signals from the circuit blocks to direct these to/from the currently active circuit block(s) as appropriate. The superimposed circuit blocks 2, 4 provide redundancy for each other, both for manufacturing defect resistance and for operational redundancy, such as providing multiple modular redundancy in safety critical environments.

Abstract: A data processing apparatus and method are provided for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within the program. Each computational subgraph has a number of input operands and produces one or more output operands. The apparatus comprises an operand store for storing the input and output operands, and processing logic for executing individual program instructions from the program. Also provided is configurable accelerator logic which, in response to reaching an execution point within the program corresponding to a sequence of individual program instructions corresponding to a computational subgraph, evaluates one or more output functions associated with the computational subgraph.