Patents by Inventor Krisztian Flautner
Krisztian Flautner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7701240Abstract: An integrated circuit 2 has a specified range of runtime-variable operating parameters. Data processing circuits 4 within the integrated circuit 2 have associated error detection and error repair mechanisms 6. When operating within a narrow typical-case range of runtime-variable operating parameters the data processing circuits 4 operate correctly and substantially without error. When operating outside of this typical-case range but inside the specified range of permitted values for the run-time variable operating parameters, then the error detection and error repair circuit 6 operate to repair the errors which occur.Type: GrantFiled: December 13, 2005Date of Patent: April 20, 2010Assignees: ARM Limited, The Regents of the University of MichiganInventors: Krisztian Flautner, David Michael Bull, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge
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Patent number: 7685404Abstract: An apparatus is provided for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within the program. A memory stores a program formed of separate program instructions. Processing logic executes respective separate program instructions from said program. Accelerator logic, in response to reaching an execution point within the program associated with a subgraph suggestion, executes a sequence of program instructions corresponding to the subgraph suggestion as an accelerated operation instead of executing the sequence of program instructions as respective separate program instructions with the processing logic.Type: GrantFiled: June 5, 2007Date of Patent: March 23, 2010Assignees: ARM Limited, University of MichiganInventors: Stuart David Biles, Krisztian Flautner, Scott Mahlke, Nathan Clark
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Patent number: 7650551Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock.Type: GrantFiled: August 16, 2007Date of Patent: January 19, 2010Assignees: ARM Limited, University of MichiganInventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge
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Publication number: 20090213673Abstract: A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.Type: ApplicationFiled: March 17, 2009Publication date: August 27, 2009Applicants: ARM Limited, University of MichiganInventors: Krisztian Flautner, David T. Blaauw, Trevo N. Mudge, Nam S. Kim, Steven M. Martin
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Patent number: 7533226Abstract: A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.Type: GrantFiled: February 14, 2006Date of Patent: May 12, 2009Assignees: ARM Limited, University of MichiganInventors: Krisztian Flautner, David T. Blaauw, Trevor N. Mudge, Nam S. Kim, Steven M. Martin
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Patent number: 7512820Abstract: Performance level selection is carried out by calculating a plurality of performance requests using a plurality of performance request calculating algorithms, combining those different performance requests to form a global performance request and then selecting a performance level in dependence upon the global performance level request. The performance request calculating algorithms can be arranged in a hierarchy with their performance requests evaluated in a sequence starting from the least dominant position in the hierarchy and moving through to the most dominant position in the hierarchy. Commands may accompany each performance level request to specify how it should be combined with other performance level requests.Type: GrantFiled: September 13, 2006Date of Patent: March 31, 2009Assignees: ARM Limited, University of MichiganInventors: Krisztian Flautner, Trevor Nigel Mudge
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Publication number: 20090049331Abstract: A method of selecting where error detection circuits should be placed within an integrated circuit uses simulation of a reference and test design with errors injected into the test design and then fan out analysis performed upon those injected errors to identify error propagation characteristics. Thus, registers at which propagated errors are highly likely to manifest themselves or which protect key architectural state, or which protect state not otherwise protected can be identified and so an efficient deployment of error detection mechanisms achieved. Within an integrated circuit output signals from inactive circuit elements may be subject to isolation gating in dependence upon a detected current state of the integrated circuit. Thus, inactive circuit elements in which soft errors occur have inappropriate output signals gated from reaching the rest of the integrated circuit and thus reducing erroneous operation.Type: ApplicationFiled: October 3, 2005Publication date: February 19, 2009Inventors: Jason Andrew Blome, Krisztian Flautner, Daryl Wayne Bradley
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Publication number: 20090015322Abstract: An integrated circuit 78 is formed of multiple layers of circuits 14, 16 superimposed to produce stacks of circuit blocks 2, 4. Stack control circuitry 18, 20 is associated with the input and output signals from the circuit blocks to direct these to/from the currently active circuit block(s) as appropriate. The superimposed circuit blocks 2, 4 provide redundancy for each other, both for manufacturing defect resistance and for operational redundancy, such as providing multiple modular redundancy in safety critical environments.Type: ApplicationFiled: January 10, 2008Publication date: January 15, 2009Applicant: ARM LimitedInventors: Krisztian Flautner, Robert Campbell Aitken, Stephen John Hill
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Publication number: 20080263332Abstract: A data processing apparatus and method are provided for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within the program. Each computational subgraph has a number of input operands and produces one or more output operands. The apparatus comprises an operand store for storing the input and output operands, and processing logic for executing individual program instructions from the program. Also provided is configurable accelerator logic which, in response to reaching an execution point within the program corresponding to a sequence of individual program instructions corresponding to a computational subgraph, evaluates one or more output functions associated with the computational subgraph.Type: ApplicationFiled: June 22, 2005Publication date: October 23, 2008Inventors: Sami Yehia, Krisztian Flautner
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Patent number: 7434072Abstract: Power management control software including power management policies is provided with those policies divided into observation code 18, 20, 22 and response code 26, 28, 30. When predetermined execution points 10, 12 within the operating system 2 are reached registered observation code 18, 20 for those execution points 10, 12 is triggered to be executed and serves to store event data within an event data store 24. At another time independent of the execution points 10, 12, the response code 26, 28, 30 is executed to read the event data from the event data store 24 and generate power control predictions and control signals therefrom.Type: GrantFiled: April 25, 2005Date of Patent: October 7, 2008Assignee: ARM LimitedInventors: Adrian Mark Peirson, Catalin Theodor Marinas, James Ian McNiven, Krisztian Flautner
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Patent number: 7406585Abstract: There is provided a system having an execution core operable to execute internal instructions. A translation buffer is operable to store a plurality of internal instruction blocks of one or more internal instructions where the internal instruction blocks are a dynamic translation of respective external instruction blocks of one or more external instructions. A remapper is responsive to an execution request for an external instruction that is within one of said external instruction blocks to identify a corresponding internal instruction block stored within said translation buffer. Thus one or more internal instructions from said corresponding internal instruction block can be supplied to execution core.Type: GrantFiled: July 1, 2003Date of Patent: July 29, 2008Assignee: ARM LimitedInventors: Andrew Christopher Rose, Krisztian Flautner
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Publication number: 20080141012Abstract: A data processing system is provided having a processor and analysing circuitry for identifying a SIMD instruction associated with a first SIMD instruction set and replacing it by a functionally-equivalent scalar representation and marking that functionally-equivalent scalar representation. The marked functionally-equivalent scalar representation is dynamically translated using translation circuitry upon execution of the program to generate one or more corresponding translated instructions corresponding to a instruction set architecture different from the first SIMD architecture corresponding to the identified SIMD instruction.Type: ApplicationFiled: September 27, 2007Publication date: June 12, 2008Applicants: ARM LIMITED, The Regents of the University of MichiganInventors: Sami Yehia, Krisztian Flautner, Nathan Clark, Amir Hormati, Scott Mahlke
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Patent number: 7363176Abstract: Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series of applied test vectors.Type: GrantFiled: December 6, 2005Date of Patent: April 22, 2008Assignee: ARM LimitedInventors: Dipesh Ishwerbhai Patel, Krisztian Flautner
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Patent number: 7356817Abstract: A method for scheduling a plurality of virtual machines includes: determining a resource requirement (Xi) for each virtual machine (VM); determining an interrupt period (Yi) for each VM; and scheduling the plurality of VMs based, at least in part, on each respective Xi and Yi.Type: GrantFiled: March 31, 2000Date of Patent: April 8, 2008Assignee: Intel CorporationInventors: Erik C. Cota-Robles, Krisztian Flautner
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Patent number: 7350055Abstract: An accelerator 120 is tightly coupled to the normal execution unit 110. The operand store, which could be a register file 130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within the instructions themselves. The sequences of individual program instructions corresponding to computational subgraphs remain within a program but can be recognized by the accelerator as suitable for acceleration and when encountered are executed by the accelerator instead of by the normal execution unit. Within such tightly coupled arrangement problems can arise due to a lack of register resources within the system. The present technique provides that at least some intermediate operand values which are generated within the accelerator, but are determined not to be referenced outside of the computational subgraph concerned, are not written to the operand store.Type: GrantFiled: January 31, 2005Date of Patent: March 25, 2008Assignee: Arm LimitedInventors: Stuart D. Biles, Krisztian Flautner, Scott Mahlke, Nathan Clark
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Patent number: 7343482Abstract: There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus comprising: a memory operable to store a program formed of separate program instructions; processing logic operable to execute respective separate program instructions from said program; and accelerator logic operable in response to reaching an execution point within said program associated with a subgraph suggestion to execute a sequence of program instructions corresponding to said subgraph suggestion as an accelerated operation instead of executing said sequence of program instructions as respective separate program instructions with said processing logic.Type: GrantFiled: January 31, 2005Date of Patent: March 11, 2008Assignees: ARM Limited, University of MichiganInventors: Stuart David Biles, Krisztian Flautner, Scott Mahlke, Nathan Clark
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Systematic and random error detection and recovery within processing stages of an integrated circuit
Patent number: 7337356Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.Type: GrantFiled: July 23, 2004Date of Patent: February 26, 2008Assignees: ARM Limited, University of MichiganInventors: Trevor Nigel Mudge, Todd Michael Austin, David Theodore Blaauw, Krisztian Flautner -
Patent number: 7330798Abstract: Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series of applied test vectors.Type: GrantFiled: April 18, 2006Date of Patent: February 12, 2008Assignee: ARM LimitedInventors: Dipesh Ishwerbhai Patel, Krisztian Flautner
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Patent number: 7321942Abstract: A performance counter accumulates a value by periodically adding a variable increment value representing the amount of work performed. The increment value can be varied in dependence upon the processor clock frequency and may be adjusted under hardware and/or software control.Type: GrantFiled: October 20, 2003Date of Patent: January 22, 2008Assignees: ARM Limited, University of MichiganInventors: Krisztian Flautner, Trevor Nigel Mudge, David Walter Flynn
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Patent number: 7318143Abstract: An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said separate program instructions of said program, an operand store operable to store operand values and an accelerator having a plurality of functional units. The accelerator executes a combined operation corresponding to a computational sub-graph of the separate program instructions by configuring individual ones of said plurality of functional units to perform particular processing operations associated with the combined operation. The accelerator executes the combined operation in dependence upon operand mapping data providing a mapping between operands of the combined operation and storage locations within said operand store and in dependence upon separately specified configuration data providing a mapping between the plurality of functional units and the particular processing operations.Type: GrantFiled: January 28, 2005Date of Patent: January 8, 2008Assignees: ARM Limited, University of MichiganInventors: Stuart D. Biles, Krisztian Flautner, Scott Mahlke, Nathan Clark