Patents by Inventor Ku-Feng Lin

Ku-Feng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12230352
    Abstract: A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.
    Type: Grant
    Filed: November 23, 2023
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ku-Feng Lin
  • Publication number: 20250031413
    Abstract: Method to implement heat dissipation multilayer and reduce thermal boundary resistance for high power consumption semiconductor devices is provided. The heat dissipation multilayer comprises a first crystalline layer that possesses a first phonon frequency range, a second crystalline layer that has a second phonon frequency range which does not overlap with the first phonon frequency range, and an amorphous layer located between the first and second crystalline layers. The amorphous layer has a third phonon frequency range that overlaps both the first and second phonon frequency ranges.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che Chi SHIH, Jhih-Rong HUANG, Han-Yu LIN, Ku-Feng YANG, Wei-Yen WOON, Szuya LIAO
  • Publication number: 20250014659
    Abstract: A method of generating an IC layout diagram includes dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two, based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the logic patterns in a storage device.
    Type: Application
    Filed: July 3, 2023
    Publication date: January 9, 2025
    Inventors: Ku-Feng LIN, Chia-En HUANG, Chieh LEE, Kazumasa UNO, Ching-Wei WU
  • Patent number: 12190986
    Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: January 7, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Lin, Jui-Che Tsai, Perng-Fei Yuh, Yih Wang
  • Publication number: 20240395290
    Abstract: A memory device includes a plurality of sense amplifiers, a plurality of memory cells, a plurality of data lines, a plurality of reference cells, and a connection line. The memory cells are coupled to a plurality of first inputs of the plurality of sense amplifiers respectively. The data lines are coupled to a plurality of second inputs of the plurality of sense amplifiers respectively. The reference cells are arranged in a plurality of columns respectively and coupled to the plurality of data line respectively. Each of the plurality of reference cells includes a plurality of resistive elements. The connection line is coupled to the plurality of data lines. In a read mode, one of the sense amplifiers is configured to access the plurality of resistive elements arranged in at least one of the plurality of columns.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ku-Feng LIN, Hiroki NOGUCHI
  • Publication number: 20240386977
    Abstract: In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first storage element coupled to a first bit line, a first transistor coupled between the first storage element and a center node, a second storage element coupled to a second bit line, a second transistor coupled between the second storage element and the center node, and a third transistor coupled between the center node and a reference node.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Lin, Perng-Fei Yuh, Meng-Sheng Chang
  • Patent number: 12148487
    Abstract: In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first storage element coupled to a first bit line, a first transistor coupled between the first storage element and a center node, a second storage element coupled to a second bit line, a second transistor coupled between the second storage element and the center node, and a third transistor coupled between the center node and a reference node.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ku-Feng Lin, Perng-Fei Yuh, Meng-Sheng Chang
  • Publication number: 20240373625
    Abstract: A semiconductor device includes a memory array comprising a plurality of transistors arranged over a plurality of rows and a plurality of columns. The plurality of rows correspond to a plurality of active regions that continuously extend along a first lateral direction, respectively, and the plurality of columns correspond to a plurality of gate structures that discontinuously extend along a second lateral direction, respectively, the first lateral direction and the second lateral direction being perpendicular to each other. A first one of the gate structures comprising a first gap cutting the first gate structure and a second one of the gate structures comprising a second gap cutting the second gate structure are disposed immediately next to each other along the first lateral direction. The first gap and an extension of the second gap are offset from each other along the second lateral direction.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kao-Cheng Lin, Ku-Feng Lin, Preciliano Ruiz, Jr., Chien-Ying Chen, Kazumasa Uno
  • Publication number: 20240363152
    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Inventors: Ku-Feng LIN, Yu-Der CHIH, Yi-Chun SHIH, Chia-Fu LEE
  • Publication number: 20240356562
    Abstract: An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.
    Type: Application
    Filed: April 15, 2024
    Publication date: October 24, 2024
    Inventors: Win-San Khwa, Hiroki Noguchi, Ku-Feng Lin
  • Patent number: 12125551
    Abstract: A memory device includes a plurality of sense amplifiers, a plurality of memory cells, a plurality of data lines, a plurality of reference cells, and a connection line. The memory cells are coupled to a plurality of first inputs of the plurality of sense amplifiers respectively. The data lines are coupled to a plurality of second inputs of the plurality of sense amplifiers respectively. The reference cells are arranged in a plurality of columns respectively and coupled to the plurality of data line respectively. Each of the plurality of reference cells includes a plurality of resistive elements. The connection line is coupled to the plurality of data lines. In a read mode, one of the sense amplifiers is configured to access the plurality of resistive elements arranged in at least one of the plurality of columns.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ku-Feng Lin, Hiroki Noguchi
  • Publication number: 20240347090
    Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
    Type: Application
    Filed: April 15, 2024
    Publication date: October 17, 2024
    Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
  • Publication number: 20240341092
    Abstract: A read-only memory (ROM) device includes a complementary field effect transistor (CFET) device which has a first semiconductor device of a first type, and a second semiconductor device of a second type different from the first type. The second semiconductor device is over or under the first semiconductor device. A first word line is electrically coupled to a gate of the first semiconductor device. A second word line is electrically coupled to a gate of the second semiconductor device. At least one bit line is electrically coupled to at least one of a first source/drain of the first semiconductor device, or a first source/drain of the second semiconductor device.
    Type: Application
    Filed: August 9, 2023
    Publication date: October 10, 2024
    Inventor: Ku-Feng LIN
  • Publication number: 20240321325
    Abstract: A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hiroki Noguchi, Ku-Feng Lin, Yih Wang
  • Publication number: 20240312497
    Abstract: A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.
    Type: Application
    Filed: May 29, 2024
    Publication date: September 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Sheng Chang, Ku-Feng Lin
  • Publication number: 20240296887
    Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Perng-Fei Yuh, Yih Wang, Ku-Feng Lin, Jui-Che Tsai, Hiroki Noguchi, Fu-An Wu
  • Publication number: 20240295603
    Abstract: A circuit includes a plurality of first inputs corresponding to a first I/O of an I/O circuit and configured to receive at least a first input signal or a second input signal; a multiplexer compressor coupled to the plurality of first inputs, and configured to alternately form a first testing path for the first input signal and a second testing path for the second input signal; a first output configured to provide a first output signal, through one of the first testing path or the second testing path, as a shifted version of a third input signal; and a second output configured to provide a second output signal, through one of the first testing path or the second testing path, as a captured version of the first input signal or the second input signal.
    Type: Application
    Filed: July 11, 2023
    Publication date: September 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-En Huang, Jui-Che Tsai, Ku-Feng Lin, Yih Wang
  • Patent number: 12080375
    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: September 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ku-Feng Lin, Yu-Der Chih, Yi-Chun Shih, Chia-Fu Lee
  • Publication number: 20240274190
    Abstract: A memory circuit includes a memory cell, a first bit line, a selection circuit, a first word line, and a first source line. The selection circuit includes a first transistor on a first level, and a second transistor on the first level or a second level. The first word line is coupled to the first or second transistor. The first source line is coupled to the first or second transistor. The first and second transistor are part of a complementary field-effect transistor. The first transistor is configured to perform a write operation of the memory cell in response to the memory cell being configured to store a first logical value. The second transistor is configured to perform a read operation of the memory cell, and the write operation of the memory cell in response to the memory cell being configured to store a second logical value.
    Type: Application
    Filed: June 19, 2023
    Publication date: August 15, 2024
    Inventors: Ku-Feng LIN, Chia-En HUANG
  • Publication number: 20240221858
    Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.
    Type: Application
    Filed: March 18, 2024
    Publication date: July 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hiroki Noguchi, Ku-Feng Lin, Yih Wang