Patents by Inventor Ku-Feng Lin
Ku-Feng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210134333Abstract: A memory device is disclosed in the present disclosure. The memory device includes multiple memory cells, multiple reference cells, and multiple sense amplifiers. The memory cells are coupled to first inputs of the sense amplifiers, respectively. The reference cells are coupled to second inputs of the sense amplifiers, respectively. The reference cells are coupled to each other.Type: ApplicationFiled: July 30, 2020Publication date: May 6, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ku-Feng LIN, Hiroki NOGUCHI
-
Publication number: 20210134352Abstract: A word line driving device of a memory device is provided. The word line driving device of the memory device includes a word line, a word line driver, and a conducting line. The word line is disposed on a first metal layer. The word line is connected to a plurality of memory cells in a memory array. The word line driver is coupled to a first node of the word line. The conducting line is disposed on a second metal layer. The first node of the word line is coupled to a first node of the conducting line and a second node of the word line is coupled to a second node of the conducting line. The distance of the second metal layer with respect to a plurality of transistors in the memory device is greater than a distance of the first metal layer with respect to the plurality of transistors in the memory device.Type: ApplicationFiled: May 19, 2020Publication date: May 6, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Ku-Feng Lin
-
Publication number: 20210135093Abstract: A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.Type: ApplicationFiled: September 25, 2020Publication date: May 6, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ku-Feng Lin
-
Patent number: 10998058Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.Type: GrantFiled: January 7, 2020Date of Patent: May 4, 2021Inventors: Yu-Der Chih, Hung-Chang Yu, Ku-Feng Lin
-
Patent number: 10957366Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.Type: GrantFiled: May 1, 2019Date of Patent: March 23, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ku-Feng Lin, Yu-Der Chih, Yi-Chun Shih, Chia-Fu Lee
-
Patent number: 10714535Abstract: A method includes forming an insulator over a substrate. The insulator includes a first electrode, a second electrode, and a resistive element between the first electrode and the second electrode. The insulator is transformed into a resistor by applying a voltage to the insulator. The resistor is electrically connected to a transistor after transforming the insulator into the resistor.Type: GrantFiled: December 21, 2018Date of Patent: July 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ku-Feng Lin, Hung-Chang Yu, Kai-Chun Lin, Yu-Der Chih
-
Publication number: 20200143896Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.Type: ApplicationFiled: January 7, 2020Publication date: May 7, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Der CHIH, Hung-Chang YU, Ku-Feng LIN
-
Publication number: 20200066335Abstract: A method for sensing logical states of memory cells in multiple segments in a memory device, each cell having a high- and low-resistance state, resulting in different cell current levels for the different resistance states. The method includes determining target reference current levels for the respective segments, at least two of the target reference current levels being different from each other; generating a reference current for each segment with the target reference current level for that segment; comparing the cell current level for each cell to the reference current level for the segment the cell is in; and determining the logical states of the memory cells based on the comparison.Type: ApplicationFiled: August 19, 2019Publication date: February 27, 2020Inventors: Yu-Der Chih, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Ku-Feng Lin
-
Publication number: 20190385656Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.Type: ApplicationFiled: June 4, 2019Publication date: December 19, 2019Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
-
Publication number: 20190362760Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.Type: ApplicationFiled: May 1, 2019Publication date: November 28, 2019Inventors: Ku-Feng LIN, Yu-Der Chih, Yi-Chun Shih, Chia-Fu Lee
-
Patent number: 10372948Abstract: A memory device is provided which comprises a memory array, a first scrambling circuit and a second scrambling circuit. The first scrambling circuit is configured to provide first scrambled data with a first scrambling pattern in response to input data. The second scrambling circuit is configured to provide second scrambled data with a second scrambling pattern in response to the first scrambled data.Type: GrantFiled: December 15, 2015Date of Patent: August 6, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kai-Chun Lin, Ku-Feng Lin, Hung-Chang Yu, Yu-Der Chih
-
Patent number: 10366765Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.Type: GrantFiled: June 28, 2017Date of Patent: July 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Der Chih, Hung-Chang Yu, Ku-Feng Lin
-
Patent number: 10281942Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: GrantFiled: February 26, 2018Date of Patent: May 7, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih
-
Publication number: 20190123107Abstract: A method includes forming an insulator over a substrate. The insulator includes a first electrode, a second electrode, and a resistive element between the first electrode and the second electrode. The insulator is transformed into a resistor by applying a voltage to the insulator. The resistor is electrically connected to a transistor after transforming the insulator into the resistor.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ku-Feng LIN, Hung-Chang YU, Kai-Chun LIN, Yu-Der CHIH
-
Patent number: 10163980Abstract: A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.Type: GrantFiled: May 26, 2016Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ku-Feng Lin, Hung-Chang Yu, Kai-Chun Lin, Yu-Der Chih
-
Publication number: 20180308554Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.Type: ApplicationFiled: June 29, 2018Publication date: October 25, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Der CHIH, Hung-Chang YU, Ku-Feng LIN
-
Publication number: 20180188756Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: ApplicationFiled: February 26, 2018Publication date: July 5, 2018Inventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih
-
Publication number: 20180174656Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.Type: ApplicationFiled: June 28, 2017Publication date: June 21, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Der CHIH, Hung-Chang YU, Ku-Feng LIN
-
Patent number: 9910451Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: GrantFiled: February 17, 2014Date of Patent: March 6, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih
-
Patent number: 9711190Abstract: A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V.Type: GrantFiled: April 10, 2014Date of Patent: July 18, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LIMITEDInventors: Kai-Chun Lin, Hung-Chang Yu, Ku-Feng Lin, Yue-Der Chih