Patents by Inventor Kuan Cheng

Kuan Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HEAT DISSIPATION DEVICE
    Publication number: 20200284522
    Abstract: A heat dissipation device includes two connected components and a flexible metal conduit. Each connected component is selected from a manifold, a quick connector, an evaporator, a condenser or a pump. The two connected components are in communication with each other through the flexible metal conduit. The use of the flexible metal conduit is effective to absorb the designing tolerance. In addition, the flexible metal conduit is recyclable.
    Type: Application
    Filed: April 10, 2019
    Publication date: September 10, 2020
    Inventors: CHIEN-AN CHEN, CHIEN-YU CHEN, TAI-WEN CHEN, KUAN-CHENG LU
  • Electrical wearable capacitive biosensor and noise artifact suppression method
    Patent number: 10729379
    Abstract: A biosensor of the invention is a capacitive noncontact sensor with two sensor channels split into a plurality of physically interdigitated symmetrical electrodes and shield sections. Two capacitive plates are electrically connected to the two sensor channels. The capacitive noncontact sensor is sized and packaged to be worn by a person to place the capacitive plates close to the skin of the person and form first and second channel input capacitors with the skin. A signal reconstruction circuit obtains a bio signal from the first and second channel input capacitors through the electrodes by reconstructing differences in the two sensor channels. The circuit includes different parasitic input capacitance in the two channels to create channel-specific outputs that depend on input coupling capacitance.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: August 4, 2020
    Assignee: The Regents of the University of California
    Inventors: Chung-Kuan Cheng, Patrick Mercier, Shih-Hung Weng
  • ELECTROSTATIC DISCHARGE PROTECTION SEMICONDUCTOR DEVICE
    Publication number: 20200235088
    Abstract: An ESD protection semiconductor device includes a substrate. A gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins having a first conductivity type are disposed in the substrate respectively at two sides of the gate set. A first doped fin is disposed in the substrate and positioned in between the source fins and spaced apart from the source fins. The first doped fin comprises a second conductivity type that is complementary to the first conductivity type. A second doped fin is formed in one of the drain fins and isolated from the one of the drain fins by an isolation structure. The second doped fin is electrically connected to the first doped fin.
    Type: Application
    Filed: April 9, 2020
    Publication date: July 23, 2020
    Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Jui Chen, Po-Ya Lai
  • Paper pickup mechanism
    Patent number: 10717615
    Abstract: A paper pickup mechanism includes a mechanical frame, a pickup roller module, a feeding roller module, a driving device, a separation roller module and an energy storage element. The mechanical frame has a platform. The pickup roller module is pivoted to and connected to the mechanical frame. The feeding roller module is pivoted to and connected to the mechanical frame. The driving device is mounted to the mechanical frame. The separation roller module is pivoted to and connected to the mechanical frame. The energy storage element is mounted between the mechanical frame and the separation roller module. When the separation roller module rotates together with the feeding roller module in a forward direction, the energy storage element accumulates energies. When more than one piece of paper is fed into the paper pickup mechanism, the energy storage element releases the energies.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: July 21, 2020
    Assignee: Foxlink Image Technology Co., Ltd.
    Inventors: Ching Jui Chen, Kuan Cheng Huang, Yung Kai Chen
  • ROTATABLE WATER-COOLING TUBE AND ELECTRONIC DEVICE WITH SAME
    Publication number: 20200221604
    Abstract: A rotatable water-cooling tube and an electronic device with the water-cooling tube are provided. The water-cooling tube includes a first tube body, a second tube body, a third tube body, a first connector and a second connector. The first tube body is in communication with the second tube body and the third tube body through the first connector and the second connector. The first tube body is rotatable with the first connector and the second connector. Consequently, the first tube body can be freely rotated to a proper position. The technology of the present invention is helpful to assemble and disassemble the heat generation component under the rotatable water-cooling tube.
    Type: Application
    Filed: February 19, 2019
    Publication date: July 9, 2020
    Inventors: CHIEN-AN CHEN, CHIEN-YU CHEN, YU-JIE LIU, KUAN CHENG LU, TAI-WEN CHEN
  • Electrostatic discharge protection semiconductor device
    Patent number: 10672759
    Abstract: An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins are formed in the substrate respectively at two sides of the gate set. At least a first doped fin is formed in the substrate at one side of the gate set the same as the source fins. A plurality of isolation structures are formed in one of the drain fins to define at least a second doped fin in the one of the drain fins. The source fins and the drain fins are of a first conductivity type. The first doped fin is of a second conductivity type that is complementary to the first conductivity type. The first doped fin and the second doped fin are electrically connected to each other.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: June 2, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Jui Chen, Po-Ya Lai
  • ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE
    Publication number: 20200144814
    Abstract: A silicon controlled rectifier includes a substrate, an N-type well, a P-type well, a gate structure, a first N-type doped region, a second N-type doped region, a first P-type doped region, a second P-type doped region, a first STI, and a second STI. The N-type well and the P-type well are disposed in the substrate. The gate structure is disposed on the P-type well. The first N-type doped region is disposed in the N-type well at one side of the gate structure. The second N-type doped region is disposed in the P-type well at another side of the gate structure. The first P-type doped region is disposed in the N-type well. The second P-type doped region is disposed in the P-type well. The first STI is between the first N-type and first P-type doped regions. The second STI is between the second N-type and second P-type doped regions.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 7, 2020
    Inventors: Shih-Che Yen, Tien-Hao Tang, Chun Chiang, Kuan-Cheng Su
  • Electrostatic discharge protection semiconductor device
    Patent number: 10629585
    Abstract: An electrostatic discharge (ESD) protection device includes a substrate, a first gate group and a second gate group on the substrate, a drain region and a fourth doped region respectively at two sides of the first gate group, a source region and the fourth doped region respectively at two sides of the second gate group, a first doped region in the substrate and surrounded by the drain region, and a second doped region in the substrate and surrounded by the fourth doped region. The drain region and the source region have a first conductivity type. The first doped region and the second doped region have a second conductivity type complementary to the first conductivity type. The drain region is electrically connected to an input/output pad. The source region is electrically connected to a ground pad. The first doped region and the second doped region are electrically connected to each other.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Chen Chang
  • Contact Openings and Methods Forming Same
    Publication number: 20200111705
    Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
  • POLISHING PAD, POLISHING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME
    Publication number: 20190381630
    Abstract: A polishing pad, a polishing apparatus and a method of manufacturing a semiconductor package using the same are provided. In some embodiments, a polishing pad includes a sub-pad portion and a top pad portion over the sub-pad portion. The top pad portion includes a plurality of grooves having a first width and a plurality of openings having a second width different from the first width, and the openings are located in a center zone of the polishing pad.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Cheng Wang, Ching-Hua Hsieh, Yi-Yang Lei
  • Contact openings and methods forming same
    Patent number: 10510593
    Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
  • Memory read circuit with N type and P type pre-charge
    Patent number: 10497405
    Abstract: A memory is described. The memory includes a storage cell. The memory also includes a read bit line coupled to the storage cell. The memory also includes at least one N type pre charge transistor coupled between the read bit line and a power supply node. The at least one N type pre-charge transistor is to pre-charge the read bit line. The memory also includes at least one P type pre charge transistor that is also coupled between the read bit line and the power supply node. The at least one P type pre-charge transistor is to pre-charge the read bit line with the at least one N type transistor.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Rajiv Kumar, Kuan Cheng Tang
  • Methods and apparatus for reducing power consumption in memory circuitry by controlling precharge duration
    Patent number: 10431269
    Abstract: Integrated circuits with volatile random-access memory cells are provided. A memory cell may be coupled to write bit lines and a read bit line. The write bit line may not be coupled to any precharge circuitry. The read bit line may only be precharged during memory access operations. In one suitable arrangement, the read bit line may be precharge immediately after an address decoding operation and before an evaluation phase. In another suitable arrangement, the read bit line may be precharged after an addressing decoding operation and in parallel with the evaluation phase. In either arrangement, a substantial amount of leakage and active power can be reduced.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: October 1, 2019
    Assignee: Altera Corporation
    Inventors: Rajiv Kumar, Wei Yee Koay, Kuan Cheng Tang
  • RGB format adjustment and reconstruction method and circuit for depth frame packing and depacking
    Patent number: 10417994
    Abstract: An RGB format adjustment method includes: obtaining subpixel values having interleaved positions from four pixels in unadjusted RGB format; obtaining subpixel values of a first pixel in an adjusted RGB format according to the obtained subpixel values, wherein the R subpixel value of the adjusted first pixel is equal to an R subpixel value of the unadjusted first pixel, the G subpixel value of the adjusted first pixel is equal to an R subpixel value of a fourth pixel in the unadjusted RGB format, and the B subpixel value of the adjusted first pixel is equal to a B subpixel value of the unadjusted first pixel; and obtaining R subpixel values, G subpixel values and B subpixel values of a second pixel, a third pixel and the fourth pixel according to the obtained subpixel values and the obtained R, G and B subpixel values of the adjusted first pixel.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 17, 2019
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Jar-Ferr Yang, Kuan-Cheng Chen
  • PAPER PICKUP MECHANISM
    Publication number: 20190248608
    Abstract: A paper pickup mechanism includes a mechanical frame, a pickup roller module, a feeding roller module, a driving device, a separation roller module and an energy storage element. The mechanical frame has a platform. The pickup roller module is pivoted to and connected to the mechanical frame. The feeding roller module is pivoted to and connected to the mechanical frame. The driving device is mounted to the mechanical frame. The separation roller module is pivoted to and connected to the mechanical frame. The energy storage element is mounted between the mechanical frame and the separation roller module. When the separation roller module rotates together with the feeding roller module in a forward direction, the energy storage element accumulates energies. When more than one piece of paper is fed into the paper pickup mechanism, the energy storage element releases the energies.
    Type: Application
    Filed: January 10, 2019
    Publication date: August 15, 2019
    Inventors: Ching Jui Chen, Kuan Cheng Huang, Yung Kai Chen
  • Grounded gate NMOS transistor having source pulled back region
    Patent number: 10366978
    Abstract: A grounded gate NMOS transistor includes a P-type substrate, P-well region in the P-type substrate, and a gate finger traversing the P-well region. The gate finger has a first spacer on a first sidewall and a second spacer on a second sidewall opposite to the first sidewall. An N+ drain doping region is disposed in the P-type substrate and is adjacent to the first sidewall of the gate finger. The N+ drain doping region is contiguous with a bottom edge of the first spacer. An N+ source doping region is disposed in the P-type substrate opposite to the N+ drain doping region. The N+ source doping region is kept a predetermined distance from a bottom edge of the second spacer. A P+ pick-up ring is disposed in the P-well region and surrounds the gate finger, the N+ drain doping region, and the N+ source doping region.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: July 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Hsiang Chang, Hou-Jen Chiu, Mei-Ling Chao, Tien-Hao Tang, Kuan-Cheng Su
  • Programmable High-Speed and Low-power Mode FPGA Memory with Configurable Floating Bitlines Scheme
    Publication number: 20190228821
    Abstract: A method for operating an SRAM of an FPGA in a high or low-power mode includes a CRAM of the FPGA storing control bits for controlling whether pages of the SRAM operate in the high or low-power mode. A control circuit of the FPGA uses the control bits, a system clock signal, and address for the pages to determine whether to operate the pages in the high or low-power mode and to control the timing for precharging and tristating read bitlines of the pages for the high and low-power modes. In the high-power mode the read bitlines are precharged longer than in the low-power mode, and in the high-power mode the read bitlines are tristated less than in the low-power mode. Precharging the read bitlines for a lesser time in the low-power mode reduces DC leakage current in the lower power mode compared to the high-power mode.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Applicant: Intel Corporation
    Inventors: Wei Yee Koay, Rajiv Kumar, Pek Mui Goh, Kuan Cheng Tang, Wei Chieh Wong
  • RGB FORMAT ADJUSTMENT AND RECONSTRUCTION METHOD AND CIRCUIT FOR DEPTH FRAME PACKING AND DEPACKING
    Publication number: 20190114992
    Abstract: An RGB format adjustment method includes: obtaining subpixel values having interleaved positions from four pixels in unadjusted RGB format; obtaining subpixel values of a first pixel in an adjusted RGB format according to the obtained subpixel values, wherein the R subpixel value of the adjusted first pixel is equal to an R subpixel value of the unadjusted first pixel, the G subpixel value of the adjusted first pixel is equal to an R subpixel value of a fourth pixel in the unadjusted RGB format, and the B subpixel value of the adjusted first pixel is equal to a B subpixel value of the unadjusted first pixel; and obtaining R subpixel values, G subpixel values and B subpixel values of a second pixel, a third pixel and the fourth pixel according to the obtained subpixel values and the obtained R, G and B subpixel values of the adjusted first pixel.
    Type: Application
    Filed: February 28, 2018
    Publication date: April 18, 2019
    Inventors: Jar-Ferr YANG, Kuan-Cheng CHEN
  • Facilitating Like-Minded User Pooling
    Publication number: 20190108599
    Abstract: Some embodiments can provide a user matching system configured to match a list of one or more users to a given user. The user matching system can be configured to employ a stage learning process including a user compatibility learning stage, an affinity learning stage, and a match optimization stage. In various exemplary implementations, various user data regarding user preferences, user traits, user behaviors, and/or any other user aspects can be collected. In those implementations, the user matching system is configured to divide the users into different user groups based on the learned user attributes, and determine similarities among users within a given group based on the user attributes. In this way, one or more users can be identified and can be suggested to the given user based on their similarities to the given user.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 11, 2019
    Inventors: Lam SUN, Boxiong Ding, Kuan-Cheng Lai
  • MEMORY READ CIRCUIT WITH N TYPE AND P TYPE PRE-CHARGE
    Publication number: 20190103140
    Abstract: A memory is described. The memory includes a storage cell. The memory also includes a read bit line coupled to the storage cell. The memory also includes at least one N type pre charge transistor coupled between the read bit line and a power supply node. The at least one N type pre-charge transistor is to pre-charge the read bit line. The memory also includes at least one P type pre charge transistor that is also coupled between the read bit line and the power supply node. The at least one P type pre-charge transistor is to pre-charge the read bit line with the at least one N type transistor.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Rajiv KUMAR, Kuan Cheng TANG