Abstract: The speech correction system includes a storage device, an audio receiver and a processing device. The processing device includes a speech recognition engine and a determination module. The storage device is configured to store a database. The audio receiver is configured to receive an audio signal. The speech recognition engine is configured to identify a key speech pattern in the audio signal and generate a candidate vocabulary list and a transcode corresponding to the key speech pattern; wherein the candidate vocabulary list includes a candidate vocabulary corresponding to the key speech pattern and a vocabulary score corresponding to the candidate vocabulary. The determination module is configured to determine whether the vocabulary score is greater than a score threshold. If the vocabulary score is greater than the score threshold, the determination module stores the candidate vocabulary corresponding to the vocabulary score in the database.

Abstract: A testing method for testing wafer level chip scale packages formed on a wafer including a wafer substrate and spaced-apart contact electrodes disposed on the wafer substrate, includes: providing a test device including a probe card formed with a plurality of parallel probe holes having a uniform cross-sectional dimension, and a plurality of probes respectively received in the probe holes and extending respectively in the probe holes along axes of the probe holes; and electrically connecting the contact electrodes to the probes. A distance between the axes of two adjacent ones of the probe holes is equal to a smallest spacing between two adjacent ones of the contact electrodes and is not greater than 0.5 mm.

Abstract: A method for improving the efficiency of reconstructing a three-dimensional model is provided. The method includes: dividing a series of different Gray code binary illumination patterns into a plurality of groups; converting binary values of Gray code binary illumination patterns in each group to a plurality of sets of two specific values to generate decimal illumination patterns corresponding to the specific values; overlapping the decimal illumination patterns in each group to a grayscale illumination pattern; using a projector to project each grayscale illumination pattern onto an object from a projection direction; using a camera to capture one or more object images of the object; reverting the object images to non-overlapping Gray code binary images corresponding to the object images; and reconstructing the depth of the object according to the non-overlapping Gray code binary images..

Abstract: An electronic test apparatus is adapted for testing an electronic component which includes a circuit substrate and a plurality of contact electrodes disposed on the circuit substrate. The electronic test apparatus includes a test seat and a plurality of spring probes. The test seat includes a metallic main body that has a first side adapted to be in contact with the circuit substrate and a second side opposite to the first side, and that is formed with a plurality of spaced-apart probe holes extending through the first and second sides, and a temperature sensor disposed in the metallic main body. The spring probes are adapted to be electrically connected to the contact electrodes and each is positioned in a respective one of the probe holes.

Abstract: A testing method for testing wafer level chip scale packages formed on a wafer including a wafer substrate and spaced-apart contact electrodes disposed on the wafer substrate, includes: providing a test device including a probe card formed with a plurality of parallel probe holes having a uniform cross-sectional dimension, and a plurality of probes respectively received in the probe holes and extending respectively in the probe holes along axes of the probe holes; and electrically connecting the contact electrodes to the probes. A distance between the axes of two adjacent ones of the probe holes is equal to a smallest spacing between two adjacent ones of the contact electrodes and is not greater than 0.5 mm.

Abstract: An electronic test apparatus is adapted for testing an electronic component which includes a circuit substrate and a plurality of contact electrodes disposed on the circuit substrate. The electronic test apparatus includes a test seat and a plurality of spring probes. The test seat includes a metallic main body that has a first side adapted to be in contact with the circuit substrate and a second side opposite to the first side, and that is formed with a plurality of spaced-apart probe holes extending through the first and second sides, and a temperature sensor disposed in the metallic main body. The spring probes are adapted to be electrically connected to the contact electrodes and each is positioned in a respective one of the probe holes.

Abstract: A method includes delivering a wafer into a process chamber, applying a thermal energy to the wafer by a heat source, and moving the heat source substantially along a longitudinal direction of the heat source with respect to the wafer. An apparatus that performs the method is also disclosed.

Abstract: An apparatus for processing a wafer includes a process chamber, a wafer support, a heat source, and a movable device. The wafer support is in the process chamber. The heat source is in the process chamber. The movable device contacts the heat source, in which the movable device is movable with respect to the wafer support.

Abstract: An apparatus for processing a wafer includes a process chamber, a wafer support, a heat source, and a movable device. The wafer support is in the process chamber. The heat source is in the process chamber. The movable device contacts the heat source, in which the movable device is movable with respect to the wafer support.

Abstract: A wideband antenna includes a grounding terminal, a first radiator disposed on a first plane, a feeding terminal formed on the first radiator, where the feeding terminal is to transmit and receive radio signals via the first radiator, and a second radiator disposed on the first plane, electrically connected to the grounding terminal, and including a part parallel to a side of the first radiator, wherein a minimum gap between the second radiator and the first radiator allows the second radiator and the first radiator to generate a coupling effect therebetween, so as to exchange radio signals between the second radiator and the first radiator.

Abstract: A semiconductor device includes a dielectric layer on a substrate, a P-type transistor having a first gate stack embedded in the dielectric layer, and an N-type transistor having a second gate stack embedded in the dielectric layer. The first gate stack includes a first metal gate electrode, a first gate dielectric layer underlying the first metal gate electrode, and a first cap layer between the first gate dielectric layer and the first metal gate electrode. The second gate stack includes a second metal gate electrode, a second gate dielectric layer underlying the second metal gate electrode, and a second cap layer between the second gate dielectric layer and the second metal gate electrode. The first and second gate stacks are adjacent, and the first and second metal gate electrodes are separated from each other by the first and second cap layers.

Abstract: A wideband antenna includes a grounding terminal, a first radiator disposed on a first plane, a feeding terminal formed on the first radiator, where the feeding terminal is to transmit and receive radio signals via the first radiator, and a second radiator disposed on the first plane, electrically connected to the grounding terminal, and including a part parallel to a side of the first radiator, wherein a minimum gap between the second radiator and the first radiator allows the second radiator and the first radiator to generate a coupling effect therebetween, so as to exchange radio signals between the second radiator and the first radiator.

Abstract: A heat dissipation control system includes an angle detection module and a control module. The heat dissipation control system is adapted for a portable electrical device having a first body and a second body. The angle detection module senses an included angle of the first body and the second body and generates an angle signal corresponding to the included angle of the first body and the second body. The control module, in response to the angle signal, generates a heat dissipation control signal according to the angle signal for enabling at least one of a first heat dissipation policy and a second heat dissipation policy.

Abstract: A semiconductor device includes a dielectric layer on a substrate, a P-type transistor having a first gate stack embedded in the dielectric layer, and an N-type transistor having a second gate stack embedded in the dielectric layer. The first gate stack includes a first metal gate electrode, a first gate dielectric layer underlying the first metal gate electrode, and a first cap layer between the first gate dielectric layer and the first metal gate electrode. The second gate stack includes a second metal gate electrode, a second gate dielectric layer underlying the second metal gate electrode, and a second cap layer between the second gate dielectric layer and the second metal gate electrode. The first and second gate stacks are adjacent, and the first and second metal gate electrodes are separated from each other by the first and second cap layers.

Abstract: A semiconductor device includes a gate structure over a substrate, a source region in the substrate, where the source region is adjacent to the gate structure. Additionally, the semiconductor device includes a drain region in the substrate, where the drain region is adjacent to the gate structure. Moreover, the semiconductor device includes a first dislocation in the substrate between the source region and the drain region. Furthermore, the semiconductor device includes a second dislocation in the substrate between the source region and the drain region, where the second dislocation is substantially parallel to the first dislocation.

Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the source and drain, forming an inter-layer dielectric (ILD) material on the substrate, removing the first dummy gate to create an ILD trench, forming a first high-k dielectric layer within the ILD trench, forming a first dummy cap portion within the ILD trench over the first high-k dielectric layer, performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer, and thereafter, replacing the first dummy cap portion with a first metal gate electrode.

Abstract: A dipole antenna is disclosed. The dipole antenna includes a feed-in terminal, a balun, a first radiator and a second radiator. The feed-in terminal is used for feeding in a radio-frequency signal. The balun is electrically connected to the feed-in terminal for driving out a return current of the dipole antenna to balance a feed-in impedance of the dipole antenna. The first radiator is electrically connected to the feed-in terminal and the balun for radiating the radio-frequency signal in a first frequency band. The second radiator is electrically connected to the first radiator, the feed-in terminal and the balun for radiating the radio-frequency signal in a second frequency band.

Abstract: A gate structure includes a gate dielectric over a substrate, and a gate electrode over the gate dielectric, wherein the gate dielectric contacts sidewalls of the gate electrode. The gate structure further includes a nitrogen-containing dielectric layer surrounding the gate electrode, and a contact etch stop layer (CESL) surrounding the nitrogen-containing dielectric layer. The gate structure further includes an interlayer dielectric layer surrounding the CESL and a lightly doped region in the substrate, the lightly doped region extends beyond an interface of the sidewalls of the gate electrode and the gate dielectric.

Abstract: A semiconductor device includes a gate structure over a substrate, a source region in the substrate, where the source region is adjacent to the gate structure. Additionally, the semiconductor device includes a drain region in the substrate, where the drain region is adjacent to the gate structure. Moreover, the semiconductor device includes a first dislocation in the substrate between the source region and the drain region. Furthermore, the semiconductor device includes a second dislocation in the substrate between the source region and the drain region, where the second dislocation is substantially parallel to the first dislocation.

Abstract: A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.