Patents by Inventor Kuan-Chung Chen
Kuan-Chung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8754477Abstract: A method of fabricating and a semiconductor device with multiple dislocation structures is disclosed. The exemplary semiconductor device includes gate structure overlying a top surface of a semiconductor substrate and a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate. The semiconductor device further includes a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer. The semiconductor device further includes a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material. The semiconductor device further includes a first stressor region disposed in the semiconductor substrate and a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material.Type: GrantFiled: October 20, 2011Date of Patent: June 17, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
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Publication number: 20140132469Abstract: A dipole antenna is disclosed. The dipole antenna includes a feed-in terminal, a balun, a first radiator and a second radiator. The feed-in terminal is used for feeding in a radio-frequency signal. The balun is electrically connected to the feed-in terminal for driving out a return current of the dipole antenna to balance a feed-in impedance of the dipole antenna. The first radiator is electrically connected to the feed-in terminal and the balun for radiating the radio-frequency signal in a first frequency band. The second radiator is electrically connected to the first radiator, the feed-in terminal and the balun for radiating the radio-frequency signal in a second frequency band.Type: ApplicationFiled: January 24, 2013Publication date: May 15, 2014Applicant: Wistron NeWeb CorporationInventors: Chih-Ming Wang, Kuan-Chung Chen, Yu-Yu Chiang
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Publication number: 20140121852Abstract: A heat dissipation control system includes an angle detection module and a control module. The heat dissipation control system is adapted for a portable electrical device having a first body and a second body. The angle detection module senses an included angle of the first body and the second body and generates an angle signal corresponding to the included angle of the first body and the second body. The control module, in response to the angle signal, generates a heat dissipation control signal according to the angle signal for enabling at least one of a first heat dissipation policy and a second heat dissipation policy.Type: ApplicationFiled: November 30, 2012Publication date: May 1, 2014Applicant: Inhon International Co., LtdInventors: Jing-Ting PENG, Cho-Yi LIN, Kuan-Chung CHEN, Shun-Chi YANG
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Publication number: 20140027843Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the source and drain, forming an inter-layer dielectric (ILD) material on the substrate, removing the first dummy gate to create an ILD trench, forming a first high-k dielectric layer within the ILD trench, forming a first dummy cap portion within the ILD trench over the first high-k dielectric layer, performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer, and thereafter, replacing the first dummy cap portion with a first metal gate electrode.Type: ApplicationFiled: October 9, 2013Publication date: January 30, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yuan Lu, Kuan--Chung Chen, Chun-Fai Cheng
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Publication number: 20130334617Abstract: A gate structure includes a gate dielectric over a substrate, and a gate electrode over the gate dielectric, wherein the gate dielectric contacts sidewalls of the gate electrode. The gate structure further includes a nitrogen-containing dielectric layer surrounding the gate electrode, and a contact etch stop layer (CESL) surrounding the nitrogen-containing dielectric layer. The gate structure further includes an interlayer dielectric layer surrounding the CESL and a lightly doped region in the substrate, the lightly doped region extends beyond an interface of the sidewalls of the gate electrode and the gate dielectric.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fung Ka HING, Haiting WANG, Han-Ting TSAI, Chun-Fai CHENG, Wei-Yuan LU, Hsien-Ching LO, Kuan-Chung CHEN
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Patent number: 8580641Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the source and drain, forming an inter-layer dielectric (ILD) material on the substrate, removing the first dummy gate to create an ILD trench, forming a first high-k dielectric layer within the ILD trench, forming a first dummy cap portion within the ILD trench over the first high-k dielectric layer, performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer, and thereafter, replacing the first dummy cap portion with a first metal gate electrode.Type: GrantFiled: July 26, 2011Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yuan Lu, Kuan-Chung Chen, Chun-Fai Cheng
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Patent number: 8535998Abstract: The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.Type: GrantFiled: March 9, 2010Date of Patent: September 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fung Ka Hing, Haiting Wang, Han-Ting Tsai, Chun-Fai Cheng, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
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Publication number: 20130187221Abstract: A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.Type: ApplicationFiled: January 23, 2012Publication date: July 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
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Publication number: 20130099314Abstract: A method of fabricating and a semiconductor device with multiple dislocation structures is disclosed. The exemplary semiconductor device includes gate structure overlying a top surface of a semiconductor substrate and a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate. The semiconductor device further includes a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer. The semiconductor device further includes a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material. The semiconductor device further includes a first stressor region disposed in the semiconductor substrate and a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material.Type: ApplicationFiled: October 20, 2011Publication date: April 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
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Patent number: 8368147Abstract: A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.Type: GrantFiled: April 16, 2010Date of Patent: February 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Fai Cheng, Ka-Hing Fung, Han-Ting Tsai, Ming-Huan Tsai, Wei-Han Fan, Hsueh-Chang Sung, Haiting Wang, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
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Publication number: 20130026579Abstract: A method for manufacturing a semiconductor device includes forming a first dummy gate on a substrate, performing a doping process to the substrate, thereby forming a source and a drain at sides of the first dummy gate, performing a first high temperature annealing to activate the source and drain, forming an inter-layer dielectric (ILD) material on the substrate, removing the first dummy gate to create an ILD trench, forming a first high-k dielectric layer within the ILD trench, forming a first dummy cap portion within the ILD trench over the first high-k dielectric layer, performing a second high-temperature annealing to reduce defects in the first high-k dielectric layer, and thereafter, replacing the first dummy cap portion with a first metal gate electrode.Type: ApplicationFiled: July 26, 2011Publication date: January 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Yuan Lu, Kuan-Chung Chen, Chun-Fai Cheng
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Publication number: 20110254105Abstract: A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.Type: ApplicationFiled: April 16, 2010Publication date: October 20, 2011Applicant: Taiwan Semiconductor Manufacturing Company. Ltd.Inventors: Chun-Fai Cheng, Ka-Hing Fung, Han-Ting Tsai, Ming-Huan Tsai, Wei-Han Fan, Hsueh-Chang Sung, Haiting Wang, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
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Publication number: 20110223752Abstract: The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.Type: ApplicationFiled: March 9, 2010Publication date: September 15, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fung Ka HING, Haiting WANG, Han-Ting TSAI, Chun-Fai CHENG, Wei-Yuan LU, Hsien-Ching LO, Kuan-Chung CHEN
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Publication number: 20070285882Abstract: A computer housing includes a first shell, and a second shell connected to the first shell by a pivot mechanism. The pivot mechanism includes two co-axial bushings mounted on the first shell respectively, and two pivot shafts mounted on the second shell respectively and each pivotally mounted in the respective bushing. Thus, the pivot shafts are inserted into the bushings simultaneously in the same direction to connect the first shell and the second shell, so that the second shell is connected to the first shell easily and quickly. In addition, the second shell is a component of the computer housing, so that it is unnecessary to manufacture a rotation case additionally, thereby decreasing the costs of fabrication.Type: ApplicationFiled: June 12, 2006Publication date: December 13, 2007Inventor: Kuan-Chung Chen
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Patent number: 7091312Abstract: The invention relates to novel nucleic acid and protein sequences from the mung bean Vigna radiata. The nucleic acid sequence, isolated from a bruchid resistant mung bean line, encodes a thionin-like protein with insecticidal properties.Type: GrantFiled: April 8, 2003Date of Patent: August 15, 2006Assignee: Academia SinicaInventors: Ching-San Chen, Kuan-Chung Chen, Cheng-Chun Kuan, Ching-Yu Lin
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Publication number: 20040005682Abstract: The invention relates to novel nucleic acid and protein sequences from the mung bean Vigna radiata. The nucleic acid sequence, isolated from a bruchid resistant mung bean line, encodes a thionin-like protein with insecticidal properties.Type: ApplicationFiled: April 8, 2003Publication date: January 8, 2004Inventors: Ching-San Chen, Kuan-Chung Chen, Cheng-Chun Kuan, Ching-Yu Lin
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Patent number: 6653463Abstract: The invention relates to novel nucleic acid and protein sequences from the mung bean Vigna radiata. The nucleic acid sequence, isolated from a bruchid resistant mung bean line, encodes a thionin-like protein with insecticidal properties.Type: GrantFiled: October 11, 2000Date of Patent: November 25, 2003Assignee: Academia SinicaInventors: Ching-San Chen, Kuan-Chung Chen, Cheng-Chun Kuan, Ching-Yu Lin