Abstract: A battery resistance measuring method, applied to a battery with a battery resistance, comprising: (a) acquiring charge variation of the battery for a measuring time interval; (b) acquiring a voltage difference between a first battery voltage and a second battery voltage for the measuring time interval, wherein the first battery voltage is a battery voltage with loading and the second battery voltage is a battery voltage without loading; and (c) computing a battery resistance according to the charge variation and the voltage difference, and updating the battery resistance to a battery resistance table of the battery. The above-mentioned steps (a), (b) and (c) may be performed by the electronic device, which can be a mobile electronic device such as a mobile phone or a plate computer.

Abstract: A thermally conductive board includes a top metal layer, a bottom metal layer, and an electrically insulating but thermally conductive layer (for simplification hereinafter referred to as “thermally conductive layer”) laminated between the top metal layer and the bottom metal layer. The thermally conductive layer includes a polymer matrix and a thermally conductive filler dispersed in the polymer matrix. The polymer matrix includes an epoxy-based composition consisting of epoxy and chlorine-containing impurities. The chlorine content of the thermally conductive layer is lower than 300 ppm.

Abstract: An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to identify crosstalk between a first signal via and a second signal via on a printed circuit board (PCB) layout, determine an area for placement of a ground via between the first signal via and the second signal via, and classify one or more regions of the PCB layout into at least one of a protective area or a non-protective area based on the area for placement of the ground via.

Abstract: A circuit board includes a metal substrate, a resin layer, an insulating layer, and a first conductive structure. The metal substrate has a first through hole, and the first through hole has a first width. A portion of the resin layer is disposed in the first through hole. The resin layer has a second through hole. The second through hole has a second width. The insulating layer is disposed on at least one surface of the metal substrate, and a portion of the insulating layer contacts the resin layer. The first conductive structure is disposed in the second through hole. The first conductive structure penetrates through the metal substrate. The first width is greater than the second width. A manufacturing method of the circuit board is also provided.

Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) providing a first layout including a plurality of cells placed therein; (b) generating a second layout by performing a first set of calculations on the first layout such that cell congestions in the first layout is eliminated from the second layout; (c) generating a third layout by performing a second set of calculations on the second layout such that the total wire length of the third layout is less than that of the second layout; and (d) iterating the operations (b) and (c) until a target layout conforming a convergence criterion.

Abstract: A thermally conductive board includes a top metal layer, a bottom metal layer, and an electrically insulating but thermally conductive layer (for simplification hereinafter referred to as “thermally conductive layer”) laminated between the top metal layer and the bottom metal layer. The thermally conductive layer satisfies a relation of I˜qa. There is an equivalence relation between I and q; “I” stands for scattering intensity; “q” stands for scattering vector, and “a” stands for the power of q. q ranges from 0.007 ??1 to 0.1 ??1, and a ranges from ?3 to ?4.

Abstract: A method for rendering data of a three-dimensional image adapted to an eye position and a display system are provided. The method is used to render the three-dimensional image to be displayed in a three-dimensional space. In the method, a three-dimensional image data used to describe the three-dimensional image is obtained. The eye position of a user is detected. The ray-tracing information between the eye position and each lens unit of a multi-optical element module forms a region of visibility (RoV) that may cover a portion of the three-dimensional image in the three-dimensional space. When coordinating the physical characteristics of a display panel and the multi-optical element module, a plurality of elemental images can be obtained. The elemental images form an integral image that records the three-dimensional image data adapted to the eye position, and the integral image is used to reconstruct the three-dimensional image.

Abstract: An electronic device is configured to execute instructions: compiling a first AI model and second AI model(s) to a first compiled file and second compiled file(s), respectively, wherein the first compiled file comprises a first data set and a first command set, and the second compiled file(s) comprises second data set(s) and second command set(s); generating light version file(s) for the AI model(s), wherein the light version file(s) comprises the second command set(s) and data patch(es); storing the first compiled file and the light version file(s) to a storage device; loading the first compiled file from the storage device to a memory; loading the light version file(s) from the storage device to the memory; generating the second data set(s) according to the first data set and the data patch(es); and executing the second AI model(s) according to the generated second data set(s) and the second command set(s) in the memory.

Abstract: A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.

Abstract: A method includes forming an epitaxial source/drain region in a substrate; forming a first inter-layer dielectric over the epitaxial source/drain region; forming a gate stack over the substrate and adjacent to the first inter-layer dielectric; forming a gate mask over the gate stack; forming a source/drain plug through the first inter-layer dielectric and electrically connected to the epitaxial source/drain region; depositing a dielectric layer over the gate mask and the first inter-layer dielectric, the dielectric layer having a different etch selectivity than the gate mask; forming a second inter-layer dielectric over the dielectric layer; etching an opening through the second inter-layer dielectric and the dielectric layer, the opening exposing the source/drain plug and the gate mask; and forming a conductive feature in the opening, the conductive feature being electrically connected to the source/drain plug.

Abstract: Provided is a filter, including a substrate layer and a near-infrared absorption layer on the substrate layer, wherein the near-infrared absorption layer includes a copper complex formed from a copper compound for supplying copper ion, phosphonric acid represented by formula 1 herein, and at least one phosphorus-containing compound represented by formulas 2 to 4 herein, wherein the OD value of the filter for the incident light wavelength from 930-950 nm is greater than 4. In the present disclosure, by setting a specific near-infrared absorption layer on the filter, the filter is able to efficiently absorb near-infrared and exhibit excellent visible light transmittance, and the burden of film post-processing can be reduced.

Abstract: Provided is an ultraviolet-absorbing resin composition, including 35 to 45 wt % of a fluorocarbon resin, 5 to 25 wt % of an isocyanate curing agent, 1 to 5 wt % of an ultraviolet absorbent, and a residual solvent accounting for the balance, based on the total weight of the ultraviolet-absorbing resin composition. Provided is also an ultraviolet-absorbing resin, an ultraviolet-absorbing structure including the same, and the method for preparing the same. The present disclosure obtains an ultraviolet-absorbing resin with a specific composition from a specific resin composition formula, and the ultraviolet-absorbing resin efficiently absorbs ultraviolet and has excellent visible light transmittance, as well as high stability.

Abstract: Implementations disclosed describe techniques and systems for calibrating parameters of a radio frequency power amplifier. The disclosed techniques include, among other things, identifying an initial power amplifier (PA) parameter set of a radio frequency (RF) module. A plurality of candidate PA parameter sets is generated. A set of error values for each of the plurality of candidate PA parameter sets is determined. A subset of the plurality of candidate PA parameter sets is identified. Each error value of the set of error values of each candidate parameter set in the subset satisfies an error threshold. A final PA parameter set is stored.

Abstract: Provided is a filter lens and a method for preparing the filter lens. The filter lens includes a copper complex, wherein the copper complex is formed from a copper compound providing copper ions, phosphoric acid represented by formula 1 herein, and at least one phosphorus-containing compound represented by formulas 2 to 4 herein, wherein the OD value of the filter lens for the incident light wavelength of 930 nm to 950 nm is greater than 4. The present disclosure enables a filter lens to have the function of filtering out near-infrared instead of using a traditional filter component and thus the size of the assembled optical lens module is reduced. The filter lens can further filter out light having other specific wavelengths, and thereby the number of lenses in the assembled optical lens module is reduced.

Abstract: Provided are a composite photosensitive element and a method for preparing a composite photosensitive element, and the composite photosensitive element includes a photosensitive element and a near-infrared absorption layer pasted on the photosensitive element, wherein the near-infrared absorption layer includes a copper complex, and the copper complex is formed from a copper compound providing copper ions, phosphoric acid represented by formula 1 herein, and at least one phosphorus-containing compound represented by formulas 2 to 4 herein, wherein the OD value of the near-infrared absorption layer for the incident light wavelength from 930-950 nm is greater than 4. The present disclosure forms a filtering film directly on the photosensitive element instead of using a traditional filter assembly to reduce the size of the assembled product. The filtering film can be further processed and shaped to have functions of micro-lens.

Abstract: Provided is a lens module with an integrated structure, including a first lens and a second lens, a first substrate and a second substrate, an optical bonding layer, a first absorption layer and a second absorption layer, wherein the first absorption layer includes a copper complex, which is formed from a copper compound, a phosphonic acid represented by formula 1 herein, and at least one phosphorus-containing compound represented by formulas 2 to 4 herein. Due to the integrated structure, the lens module can be reduced in size. The manufacturing process is simplified because no assembly process is required. The lens module of the present disclosure exhibits high transmittance for visible light and low transmittance for near-infrared, showing an excellent near-infrared cut-off effect. In addition, while the incident light irradiates the lens module at different angles, the transmittance curve only is slightly shifted.

Abstract: An integrated circuit is provided which includes a first complementary field-effect transistor and a second complementary field-effect transistor. The first complementary field-effect transistor includes at least two first transistors respectively located on a first layer and a second layer. The second complementary field-effect transistor is disposed adjacent to the first complementary field-effect transistor. The second complementary field-effect transistor includes at least two second transistors respectively located on the first layer and the second layer. Type of one of the at least two first transistors located on the first layer is different from type of one of the at least two second transistors located on the first layer.

Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout; (b) generating a second layout by performing a first set of calculations on the first layout such that a total wire length of the second layout is less than that of the first layout; (c) generating a third layout by performing a second set of calculations on the second layout such that cell congestions in the second layout is eliminated from the third layout; (d) generating a fourth layout by performing a third set of calculations on the third layout such that the total wire length of the fourth layout is less than that of the third layout; and (e) iterating the operations (c) and (d) until a target layout conforms to a convergence criterion.

Abstract: Disclosed is a method of manufacturing a three dimensional (3D) metal-insulator-metal (MIM) capacitor in the back end of line, which can provide large and tunable capacitance values and meanwhile, does not interfere with the existing BEOL fabrication process.

Abstract: A graphics system is provided. The graphics system includes a frame buffer, a timing controller, and a processing unit. The processing unit generating an output video frame based on a raw video frame. The output video frame includes the main window and a picture-in-picture window overlaid on the main window, and the picture-in-picture window is generated by zooming in a target region of the main window. The timing controller is configured to generates a first vertical synchronization signals to control the input timing for the processing unit to write the raw video frame into the frame buffer, and generate a second vertical synchronization signal to control an output timing for the processing unit to read the raw video frame from the frame buffer and generating the output video frame, such that specific timing conditions are met.