Abstract: The semiconductor device structures are provided. The semiconductor device structure includes a gate stack structure formed on a substrate and an isolation structure formed in the substrate. The semiconductor device structure further includes a source/drain stressor structure formed between the gate stack structure and the isolation structure and a metal silicide layer formed on the source/drain stressor structure. A portion of the metal silicide layer is below a top surface of the isolation structure.

Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes first circuit elements where a first portion of the first circuit elements has a defect. The second layer includes second circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second circuit elements for mitigating the defect.

Abstract: A foldable structure of an electric vehicle is disclosed. In the foldable structure, a frame defines a stowing space, and includes a connection base and a rotatable seat. The connection base has a chute and the seat includes a link rod. The wheel part includes two wheel casings, a tire and a driving device, and a containing space is formed between the wheel casings for containing the tire and the driving device. The wheel casings has a rotator cap protruded at tops thereof, and the rotator cap has an axle hole longitudinally cut therethrough, and the rotator cap is pivotally connected with the rotatable seat by the axle hole, whereby the link rod can be slid into the chute, and the two wheel casings and the tire can be laterally rotated into the stowing space, such that the electric vehicle can just occupy smaller space.

Abstract: A setting method of a counting flow path is applied to an image monitoring system and a related computer-readable media. The counting flow path is utilized to determine whether an object passes through a monitoring area. The setting method includes drawing two boundaries on a video frame correlative to the monitoring area to define the counting flow path, detecting relative position between a first angle control point and a second angle control point of the counting flow path, adjusting an angle formed by virtual lines stretching from the boundaries according to the relative position between the said angle control points, and utilizing an initial point and a final point detected by the counting flow path while the objects moves into or out of the counting flow path to determine whether the object passes through the counting flow path.

Abstract: A method for transmitting and displaying an object tracking information includes steps of capturing an image by a camera, wherein an object exists in the image; analyzing the image by the camera to obtain a 3D world coordinate information of the object; transmitting a projection matrix and the 3D world coordinate information to a display device by the camera; using the projection matrix to convert the 3D world coordinate information into a 2D image coordinate information by the display device; and displaying a pattern corresponding to the object according to the 2D image coordinate information by the display device.

Abstract: A transformer structure comprising a winding stand, a first coil, two second coils, and an iron core set. The first coil winds on the winding portion of the winding stand, and the first coil connects to the first pins electrically. The second coils are two metal sheets having electrical conductivity, the two second coils are provided with a ring body and two second pins respectively, the two second coils being arranged on the side edge of the winding portion of the winding stand. The iron core set is arranged on the winding stand, and the iron core set passes internally through the first coil and the two second coils. As a result, the DC resistance is decreased and the power consumption is reduced accordingly, improving the temperature rising problem.

Abstract: An endoscopic surgical instrument is revealed herein to comprise a handle, a hollow tube fitted at a front end of the handle and having an oblique opening at a distal end thereof, a repair device fitted inside the hollow tube and having a cutting portion partially exposed to the oblique opening, and an electrocautery device fitted on an end surface of the oblique opening of the hollow tube.

Abstract: The semiconductor device structures are provided. The semiconductor device structure includes a gate stack structure formed on a substrate and an isolation structure formed in the substrate. The semiconductor device structure further includes a source/drain stressor structure formed between the gate stack structure and the isolation structure and a metal silicide layer formed on the source/drain stressor structure. A portion of the metal silicide layer is below a top surface of the isolation structure.

Abstract: A circuit including a first switch receiving an input reference voltage, a second switch receiving an input testing voltage, the first switch and the second switch are electrically connected in parallel. The circuit further includes a first capacitor electrically connected in series with the first switch and the second switch. The circuit further includes a feedback stage comprising a feedback inverter electrically connected in parallel with a feedback switch, where the feedback stage is electrically connected in series with the first capacitor. The circuit further includes a first inverter electrically connected in series to the feedback stage, and a third switch electrically connected in series with the first inverter. The circuit further includes a second inverter electrically connected in parallel to a third inverter, the second inverter and the third inverter are electrically connected in series to the third switch, and the third inverter outputs a first output signal.

Abstract: Methods for forming a semiconductor device structure are provided. The method includes providing a substrate and forming an isolation structure in the substrate. The method also includes forming a gate stack structure on the substrate and etching a portion of the substrate to form a recess in the substrate, and the recess is adjacent to the gate stack structure. The method includes forming a stressor layer in the recess, and a portion of the stressor layer is grown along the (311) and (111) crystal orientations.

Abstract: A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.

Abstract: An interposer element in a multidimensional integrated circuit with stacked elements has one or more conductors, especially power supply lines, coupled through decoupling networks defining low impedance shunts for high frequency signals to ground. The interposer has successive tiers including silicon, metal and dielectric deposition layers. The decoupling network for a conductor has at least one and preferably two reactive transmission lines. A transmission line has an inductor in series with the conductor and parallel capacitances at the inductor terminals. The inductors are formed by traces in spaced metal deposition layers forming coil windings and through vias connecting between layers to permit conductor crossovers. The capacitances are formed by MOScaps in the interposer layers. An embodiment has serially coupled coils with capacitances at the input, output and junction between the coils, wherein the coils are magnetically coupled to form a transformer.

Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes first circuit elements where a first portion of the first circuit elements has a defect. The second layer includes second circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second circuit elements for mitigating the defect.

Abstract: Methods for forming a semiconductor device structure are provided. The method includes providing a substrate and forming an isolation structure in the substrate. The method also includes forming a gate stack structure on the substrate and etching a portion of the substrate to form a recess in the substrate, and the recess is adjacent to the gate stack structure. The method includes forming a stressor layer in the recess, and a portion of the stressor layer is grown along the (311) and (111) crystal orientations.

Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes a first plurality of circuit elements where a first portion of the first plurality of circuit elements has defects. The second layer includes a second plurality of circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second plurality of circuit elements for mitigating the defects.

Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stack structure. The semiconductor device structure further includes an isolation structure formed in the substrate and a source/drain stressor structure formed adjacent to the isolation structure. The source/drain stressor structure includes a capping layer which is formed along the (311) and (111) crystal orientations.

Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stack structure. The semiconductor device structure further includes an isolation structure formed in the substrate and a source/drain stressor structure formed adjacent to the isolation structure. The source/drain stressor structure includes a capping layer which is formed along the (311) and (111) crystal orientations.

Abstract: A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.

Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.

Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.